Renesas SH7781 - Manual (Page 725)

14. Direct Memory Access Controller (DMAC)
Rev.1.00 Jan. 10, 2008 Page 695 of 1658
REJ09B0261-0100
• DMARS1
Bit Bit Name
Initial
Value R/W Descriptions
15
14
13
12
11
10
C3MID5
C3MID4
C3MID3
C3MID2
C3MID1
C3MID0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
Transfer request source module ID5 to ID0 for DMA
channel 3 (MID)
See table 14.3.
9
8
C3RID1
C3RID0
0
0
R/W
R/W
Transfer request source register ID1 and ID0 for DMA
channel 3 (RID)
See table 14.3.
7
6
5
4
3
2
C2MID5
C2MID4
C2MID3
C2MID2
C2MID1
C2MID0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
Transfer request source module ID5 to ID0 for DMA
channel 2 (MID)
See table 14.3.
1
0
C2RID1
C2RID0
0
0
R/W
R/W
Transfer request source register ID1 and ID0 for DMA
channel 2 (RID)
See table 14.3.