Renesas SH7781 - Manual (Page 769)

15. Clock Pulse Generator (CPG)
Rev.1.00 Jan. 10, 2008 Page 739 of 1658
REJ09B0261-0100
15.4 Register Descriptions
Table 15.5 lists the registers. Table 15.6 shows the register states in each processing mode.
Table 15.5 Register Configuration
Register Name Abbreviation R/W P4 Address
Area 7
Address Access
Size Sync
Clock
Frequency control register 0 FRQCR0 R/W H'FFC8 0000 H'1FC8 0000 32 Pck
Frequency control register 1 FRQCR1 R/W H'FFC8 0004 H'1FC8 0004 32 Pck
Frequency display register 1 FRQMR1 R H'FFC8 0014 H'1FC8 0014 32 Pck
Sleep control register SLPCR R/W H'FFC8 0020 H'1FC8 0020 32 Pck
PLL control register PLLCR R/W H'FFC8 0024 H'1FC8 0024 32 Pck
Standby control register 0* MSTPCR0 R/W H'FFC8 0030 H'1FC8 0030 32 Pck
Standby control register 1* MSTPCR1 R/W H'FFC8 0034 H'1FC8 0034 32 Pck
Standby display register* MSTPMR R H'FFC8 0044 H'1FC8 0044 32 Pck
Note: * For details on the standby control registers, see section 17, Power-Down Mode.