Renesas SH7781 User Manual
Page 81
3. Instruction Set
Rev.1.00 Jan. 10, 2008 Page 51 of 1658
REJ09B0261-0100
Addressing
Mode
Instruction
Format
Effective Address Calculation Method
Calculation
Formula
Immediate
#imm:8
8-bit immediate data imm of TST, AND, OR, or XOR
instruction is zero-extended.
—
#imm:8
8-bit immediate data imm of MOV, ADD, or CMP/EQ
instruction is sign-extended.
—
#imm:8
8-bit immediate data imm of TRAPA instruction is
zero-extended and multiplied by 4.
—
Note: For the addressing modes below that use a displacement (disp), the assembler descriptions
in this manual show the value before scaling (
Ч1, Ч2, or ×4) is performed according to the
operand size. This is done to clarify the operation of the LSI. Refer to the relevant
assembler notation rules for the actual assembler descriptions.
@ (disp:4, Rn)
; Register indirect with displacement
@ (disp:8, GBR) ; GBR indirect with displacement
@ (disp:8, PC)
; PC-relative with displacement
disp:8,
disp:12 ;
PC-relative