Renesas SH7781 User Manual
Page 659
13. PCI Controller (PCIC)
Rev.1.00 Jan. 10, 2008 Page 629 of 1658
REJ09B0261-0100
(28)
PCI PIO Data Register (PCIPDR)
By reading or writing to this register, a configuration cycle is generated on the PCI bus. For
details, see section 13.4.5 (2), Configuration Space Access.
SH R/W:
PCI R/W:
SH R/W:
PCI R/W:
16
17
18
19
20
21
22
23
24
25
26
27
28
29
31
30
Bit:
Initial value:
PDR
PDR
0
1
2
3
4
5
6
7
8
9
10
11
12
13
15
14
Bit:
Initial value:
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit Bit
Name
Initial
Value R/W Description
31 to 0
PDR
H'xxxx
xxxx
SH: R/W
PCI:
⎯
PCI PIO Data Register
By reading or writing to this register, a configuration
cycle is generated on the PCI bus.