Renesas SH7781 - Manual (Page 806)

16. Watchdog Timer and Reset (WDT)
Rev.1.00 Jan. 10, 2008 Page 776 of 1658
REJ09B0261-0100
(3) Power-On Reset Caused by PRESET Input in Sleep Mode
It is necessary to ensure the PLL oscillation settling time when a power-on reset is initiated by a
low level input on the
PRESET pin during sleep mode.
The timing of reset state indication on the STATUS[1:0] pins is asynchronous. The timing of
indicating normal operation is synchronous with the peripheral clock (Pck), and is therefore
asynchronous with the clocks input from the EXTAL pin and the CLKOUT pin.
CLKOUT
output
STATUS[1:0]
output
HH (reset) HH (reset) LL (normal) HL (sleep)
PLL oscillation
settling time Reset holding time
PRESET
input
EXTAL
input
CLKOUTENB
output
Figure 16.5 STATUS Output by Power-On Reset Caused by
PRESET Input
in Sleep Mode