Renesas SH7781 - Manual (Page 1456)

28. General Purpose I/O Ports (GPIO)
Rev.1.00 Jan. 10, 2008 Page 1426 of 1658
REJ09B0261-0100
28.2.25 Port J Data Register (PJDR)
PJDR is an 8-bit readable/writable register that stores port J data.
0 1 2 3 4 5 6 7
x x
PJ0DT PJ1DT PJ2DT PJ3DT PJ4DT PJ5DT PJ6DT PJ7DT
x x x x x x
R/W R/W R/W R/W R/W R/W R/W R/W
Bit:
Initial value:
R/W:
Bit Bit Name
Initial
value R/W Description
7 PJ7DT Pin input R/W
6 PJ6DT Pin input R/W
5 PJ5DT Pin input R/W
4 PJ4DT Pin input R/W
3 PJ3DT Pin input R/W
2 PJ2DT Pin input R/W
1 PJ1DT Pin input R/W
These bits store output data of a pin which is used as a
general-purpose output port. When the pin functions as
a general-purpose output port, reading the port will read
out the value of the corresponding bit of this register.
When the pin functions as a general-purpose input port,
reading the port will read out the status of the
corresponding pin.
0 PJ0DT Pin input R/W