27 port l data register (pldr) – Renesas SH7781 User Manual
Page 1458
28. General Purpose I/O Ports (GPIO)
Rev.1.00 Jan. 10, 2008 Page 1428 of 1658
REJ09B0261-0100
28.2.27
Port L Data Register (PLDR)
PLDR is an 8-bit readable/writable register that stores port L data.
0
1
2
3
4
5
6
7
x
x
x
x
x
x
x
x
PL0DT
PL1DT
PL2DT
PL3DT
PL4DT
PL5DT
PL6DT
PL7DT
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit:
Initial value:
R/W:
Bit Bit
Name
Initial
value R/W Description
7 PL7DT
Pin
input
R/W
6 PL6DT
Pin
input
R/W
5 PL5DT
Pin
input
R/W
4 PL4DT
Pin
input
R/W
3 PL3DT
Pin
input
R/W
2 PL2DT
Pin
input
R/W
These bits store output data of a pin which is used as a
general-purpose output port. When the pin functions as
a general-purpose output port, reading the port will read
out the value of the corresponding bit of this register.
When the pin functions as a general-purpose input port,
reading the port will read out the status of the
corresponding pin.
1 PL1DT
Pin
input
R/W
0 PL0DT
Pin
input
R/W