Renesas SH7781 User Manual
Page 280
9. On-Chip Memory
Rev.1.00 Jan. 10, 2008 Page 250 of 1658
REJ09B0261-0100
9.2.3
OL memory Transfer Source Address Register 1 (LSA1)
When MMUCR.AT = 0 or RAMCR.RP = 0, the LSA1 specifies the transfer source physical
address for block transfer to page 1A or 1B in the OL memory.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Bit :
0
0
0
Initial value :
R
R
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
L1SADR
L1SADR
L1SSZ
R/W
R/W
R/W
R/W
R/W
R/W
R/W:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Bit :
0
0
0
0
Initial value :
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W:
Bit Bit
Name
Initial
Value R/W
Description
31 to 29 —
All 0
R
Reserved
For read/write in these bits, refer to General
Precautions on Handling of Product.
28 to 10 L1SADR
Undefined R/W
OL memory Page 1 Block Transfer Source Address
When MMUCR.AT = 0 or RAMCR.RP = 0, these bits
specify transfer source physical address for block
transfer to page 1A or 1B in the OL memory.
9 to 6
—
All 0
R
Reserved
For read/write in these bits, refer to General
Precautions on Handling of Product.