3) intstr2 – Renesas SH7781 User Manual
Page 1222
24. Multimedia Card Interface (MMCIF)
Rev.1.00 Jan. 10, 2008 Page 1192 of 1658
REJ09B0261-0100
(3)
INTSTR2
Bit:
Initial value:
R/W:
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
R
FRDY
_TU
FRDYI
R
R
R
R
R
R
R/W
—
—
—
—
—
—
—
Bit Bit
Name
Initial
Value R/W Description
Interrupt
output
7 to 2
⎯ All
0
R
Reserved
These bits are always read as 0. The write
value should always be 0.
⎯
1 FRDY_TU
Undefined
R
FIFO Ready Flag
Regardless of set values of DMAEN and
FRDYIE, this bit is read as 0 when FIFO
data amount matches the asserting
condition set in DMACR[2:0], and
otherwise, read as 1.
⎯
0
FRDYI
0
R/W
FIFO Ready Interrupt Flag
0: No interrupt
[Clearing condition]
Write 0 after reading FRDYI = 1.
(Writing 1 is invalid)
1: Interrupt requested
[Setting condition]
When remained FIFO data does not match
the assert condition set in DMACR while
DMAEN = 1 and FRDYIE = 1.
Note: FRDYI will be set on the setting
condition after clearing. To clear it,
disable the flag setting by FRDYIE in
INTCR2.
FRDY