11 receive fifo data count register n (scrfdr) – Renesas SH7781 User Manual
Page 1095
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21. Serial Communication Interface with FIFO (SCIF)
Rev.1.00 Jan. 10, 2008 Page 1065 of 1658
REJ09B0261-0100
21.3.11
Receive FIFO Data Count Register n (SCRFDR)
SCRFDR is a 16-bit register that indicates the number of receive data bytes stored in SCFRDR.
SCRFDR can always be read from the CPU.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
15
14
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R0
R1
R2
R3
R4
R5
R6
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
BIt:
Initial value:
R/W:
Bit Bit
Name
Initial
Value R/W
Description
15 to 7
—
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
6 to 0
R6 to R0
All 0
R
These bits show the number of receive data bytes in
SCFRDR. A value of H'00 indicates that there is no
receive data, and a value of H'40 indicates that
SCFRDR is full of receive data.
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