3 interrupt event register (intevt) – Renesas SH7781 User Manual
Page 122
5. Exception Handling
Rev.1.00 Jan. 10, 2008 Page 92 of 1658
REJ09B0261-0100
5.2.3
Interrupt Event Register (INTEVT)
The interrupt event register (INTEVT) consists of a 14-bit exception code. The exception code is
set automatically by hardware when an exception occurs. INTEVT can also be modified by
software.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Bit:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Initial value:
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R/W
INTCODE
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W:
Bit:
Initial value:
R/W:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
R
R
R/W
R/W
R/W
R/W
R/W
R/W
Bit Bit
Name
Initial
Value R/W
Description
31 to 14
⎯ All
0
R
Reserved
For details on reading/writing this bit, see General
Precautions on Handling of Product.
13 to 0
INTCODE
Undefined R/W Exception
Code
The exception code for an interrupt is set. For details,
see table 5.3.