Renesas SH7781 - Manual (Page 210)

7. Memory Management Unit (MMU)
Rev.1.00 Jan. 10, 2008 Page 180 of 1658
REJ09B0261-0100
PPN[28:10]
PPN[28:10]
PPN[28:10]
ESZ[3:0]
ESZ[3:0]
ESZ[3:0]
SH
SH
SH
C
C
C
EPR[5:0]
EPR[5:0]
EPR[5:0]
ASID[7:0]
ASID[7:0]
ASID[7:0]
VPN[31:10]
VPN[31:10]
VPN[31:10]
V
V
V
Entry 0
Entry 1
Entry 2
D
D
D
WT
WT
WT
PPN[28:10] ESZ[3:0] SH C EPR[5:0] ASID[7:0] VPN[31:10] V Entry 63 D WT
− − − V C D SH WT
Write
− ASID
PTEH PTEL
LRUI − URB − URC SV ME − − TI AT
MMUCR
VPN PPN −
PTEA
EPR ESZ −
Entry specification
SQMD
Figure 7.17 Operation of LDTLB Instruction (TLB Extended Mode)
7.5.4 Hardware ITLB Miss Handling
In an instruction access, this LSI searches the ITLB. If it cannot find the necessary address
translation information (ITLB miss occurred), the UTLB is searched by hardware, and if the
necessary address translation information is present, it is recorded in the ITLB. This procedure is
known as hardware ITLB miss handling. If the necessary address translation information is not
found in the UTLB search, an instruction TLB miss exception is generated and processing passes
to software.