Document Outline

• CS4953x4/CS4970x4 System Designer's Guide
  • Contents
  • Figures
  • Tables
• Preface
  • P.1 Introduction to CS4953x4/CS4970x4 System Designer’s Guide
  • P.2 Overview of the CS4953x4/CS4970x4 DSP
    • P.2.1 Chip Features
  • P.3 CS4953x4/CS4970x4 Chip Functional Overview
    • P.3.1 DSP Core
    • P.3.2 Security Extension module
    • P.3.3 Debug Controller (DBC)
    • P.3.4 Digital Audio Output (DAO1, DAO2) Controller
    • P.3.5 Digital Audio Input (DAI1) Controller
    • P.3.6 Compressed Data Input / Digital Audio Input (DAI2) Controller
    • P.3.7 Direct Stream Digital (DSD) Controller
    • P.3.8 General Purpose I/O
    • P.3.9 Serial Control Ports (SPI™ or I2C™ Standards)
    • P.3.10 SDRAM Controller
    • P.3.11 DMA Controller
    • P.3.12 Timers
    • P.3.13 Clock Manager and PLL
    • P.3.14 Programmable Interrupt Controller
  • P.4 Firmware Overview
    • P.4.1 Robust DSP Manager Firmware API
    • P.4.2 DSP Condenser
  • P.5 CS40700x Pin Descriptions
    • P.5.1 Power and Ground
      • P.5.1.1 Power
      • P.5.1.2 Ground
      • P.5.1.3 Decoupling
    • P.5.2 PLL Filter
      • P.5.2.1 Analog Power Conditioning
      • P.5.2.2 PLL
    • P.5.3 Clocking
    • P.5.4 Control
      • P.5.4.1 Operational Mode
  • P.6 CS4970x4 Pin Assignments
  • P.7 CS4953x4 Pin Assignments
• 1 Operational Modes
  • 1.1 Overview
    • 1.1.1 Supported Serial Flash Devices
  • 1.2 Operational Mode Selection
  • 1.3 Booting the DSP in Master Boot Mode
    • 1.3.1 Performing a Master Boot
      • 1.3.1.1 Master Boot Protocol
      • 1.3.1.2 Messages Read from CS4953x4/CS4970x4
• 2 Serial Communication Mode
  • 2.1 Introduction
  • 2.2 Communication Using the Serial Control Port
  • 2.3 Serial Control Port Configuration
  • 2.4 SPI Port
    • 2.4.1 SPI System Bus Description
    • 2.4.2 SPI Bus Dynamics
      • 2.4.2.1 SCP1_BSY Behavior
    • 2.4.3 SPI Messaging
      • 2.4.3.1 Performing a Serial SPI Write
      • 2.4.3.2 SPI Write Protocol
      • 2.4.3.3 Performing a Serial SPI Read
      • 2.4.3.4 SPI Read Protocol
      • 2.4.3.5 SCP1_IRQ Behavior
  • 2.5 I2C Port
    • 2.5.1 I2C System Bus Description
    • 2.5.2 I2C Bus Dynamics
    • 2.5.3 I2C Messaging
      • 2.5.3.1 SCP1_BSY Behavior
      • 2.5.3.2 Performing a Serial I2C Write
      • 2.5.3.3 I2C Write Protocol
      • 2.5.3.4 Performing a Serial I2C Read
      • 2.5.3.5 I2C Read Procedure
      • 2.5.3.6 SCP1_IRQ Behavior
• 3 Audio Input Interfaces
  • 3.1 Introduction
  • 3.2 Digital Audio Input Port Description
    • 3.2.1 DAI Pin Description
    • 3.2.2 Supported DAI Functional Blocks
    • 3.2.3 BDI Port
    • 3.2.4 Digital Audio Formats
      • 3.2.4.1 I2S Format
      • 3.2.4.2 Left-Justified Format
  • 3.3 DAI Hardware Configuration
    • 3.3.1 DAI Hardware Naming Convention
  • 3.4 Digital Audio Input Port Description
    • 3.4.1 DSD Pin Description
    • 3.4.2 Supported DSD Functional Blocks
• 4 Audio Output Interface
  • 4.1 Introduction
  • 4.2 Digital Audio Output Port Description
    • 4.2.1 DAO Pin Description
    • 4.2.2 Supported DAO Functional Blocks
    • 4.2.3 DAO Interface Formats
      • 4.2.3.1 I2S Format
      • 4.2.3.2 Left-Justified Format
      • 4.2.3.3 One-line Data Mode Format (Multichannel)
    • 4.2.4 DAO Hardware Configuration
    • 4.2.5 DAO Hardware Naming Convention
    • 4.2.6 S/PDIF Transmitter
• 5 External Memory Interfaces
  • 5.1 SDRAM Controller
    • 5.1.1 SDRAM Controller Interface
    • 5.1.2 SDRAM Interface Signals
    • 5.1.3 Configuring SDRAM Parameters
  • 5.2 SPI Flash Interface
• 6 System Design Requirements for SPDIF and HDMI™ Technology Interfaces
  • 6.1 Introduction
    • 6.1.1 Designing a SPDIF Input Interface
      • 6.1.1.1 SPDIF Clocking
    • 6.1.2 Designing an HDMI Input Interface
      • 6.1.2.1 HDMI Clocking
      • 6.1.2.2 Decoding Stream Types Over HDMI
    • 6.1.3 Other System Design Considerations
• 7 Overview of Common Firmware Modules
  • 7.1 Introduction
  • 7.2 CS4953x4/CS4970x4 Firmware
    • 7.2.1 Firmware Modules
    • 7.2.2 Overlay Architecture
  • 7.3 Firmware Messaging
    • 7.3.1 Communication Overview
    • 7.3.2 Writing to the DSP
    • 7.3.3 Solicited Read
    • 7.3.4 Unsolicited Read
    • 7.3.5 Index Configuration
    • 7.3.6 Unsolicited Messages from DSP to the Host Microcontroller
    • 7.3.7 DSP_AUTODETECT_MSG
    • 7.3.8 DSP_LAST_ACCN_MSG
  • 7.4 CS4953x4/CS4970x4 DSP Manager API Description
    • 7.4.1 Microcontroller Interface (API)
    • 7.4.2 DSP_CFG_xxx Registers
      • 7.4.2.1 Using DSP Condenser to Change/Load Firmware Modules
      • 7.4.2.2 Using DSP Condenser to Change the Audio Input Source
    • 7.4.3 Status Registers
  • 7.5 Legacy API Still in Use
    • 7.5.1 Legacy Audio Manager
  • 7.6 OS Firmware Module
    • 7.6.1 Overview
    • 7.6.2 OS-A and OS-B Module Manager
    • 7.6.3 Other DSP Audio Manager Registers
• 8 DSP Condenser
  • 8.1 Overview
    • 8.1.1 Purpose of DSP Condenser
  • 8.2 Development Flow
  • 8.3 Elements of a Project
    • 8.3.1 General Page
    • 8.3.2 Search paths Page
    • 8.3.3 Audio sources Page
    • 8.3.4 Sample rates Page
    • 8.3.5 Firmware components Page
    • 8.3.6 PPM modes Page
    • 8.3.7 Stream types Page
    • 8.3.8 Power-up state Page
    • 8.3.9 WAV update Page
  • 8.4 Creating a Condenser Project using a Model
    • 8.4.1 Using the Wizard to Create a Project
  • 8.5 Creating a Flash Image
    • 8.5.1 How to create an image
    • 8.5.2 What Does the Image Contain?
  • 8.6 Using DSP Condenser
    • 8.6.1 How to use DSP Composer with DSP Condenser
      • 8.6.1.1 Best Practices
      • 8.6.1.2 Creating Projects
    • 8.6.2 Capturing Snapshots
  • 8.7 Creating a Flash Image
    • 8.7.1 SPI Flash Image Format
      • 8.7.1.1 Master Boot Image (egg.img)
      • 8.7.1.2 Updatable Flash Image
      • 8.7.1.3 DSP State Space
      • 8.7.1.4 Microcontroller Unit (MCU) Scratchpad
    • 8.7.2 Creating a Serial Flash Image Manually
      • 8.7.2.1 Using the DSP Condenser Wizard to Create a Serial Flash Image
      • 8.7.2.2 Making Snapshots of a Change
      • 8.7.2.3 Integrating the Snapshots into the Flash Image
      • 8.7.2.4 Exploring the Build Outputs
    • 8.7.3 Field Upgrade of Flash Image
      • 8.7.3.1 Steps for Carrying Out a Field Upgrade of Flash Image
  • 8.8 DSP Response after Master Boot.
  • 8.9 Host Activity
• 9 Using Runtime Condenser
  • 9.1 DSP Condenser Runtime Application
    • 9.1.1 Usage
      • 9.1.1.1 Standard Launch
  • 9.2 Runtime GUI Current Project
    • 9.2.1 Connection Group
      • 9.2.1.1 Connection to Board Button
      • 9.2.1.2 Connection Status Led
      • 9.2.1.3 Use JP1 Checkbox1
    • 9.2.2 Command Group
      • 9.2.2.1 Read DSP Button
      • 9.2.2.2 Reset DSP Button
      • 9.2.2.3 Auto Read Checkbox
      • 9.2.2.4 Command Field
        • 9.2.2.4.1 Hexadecimal Command
        • 9.2.2.4.2 Configuration File Commmand
        • 9.2.2.4.3 Comments
      • 9.2.2.5 Browse Button
    • 9.2.3 DSP Status Group
      • 9.2.3.1 DSP Reset LED
      • 9.2.3.2 Interrupt Request LED
      • 9.2.3.3 Busy LED
    • 9.2.4 Log Window
      • 9.2.4.1 Color Coding
      • 9.2.4.2 Menu Items
    • 9.2.5 Source Selection Group
      • 9.2.5.1 Input Source Combo Box
      • 9.2.5.2 Apply Button
      • 9.2.5.3 Reset DSP When Changing Source Checkbox
    • 9.2.6 Source Status Group
      • 9.2.6.1 Manual Refresh Button
      • 9.2.6.2 Auto Refresh Button
      • 9.2.6.3 Auto Read Checkbox
      • 9.2.6.4 Source Status Text Fields
    • 9.2.7 DSP Manager API Group
      • 9.2.7.1 Source
      • 9.2.7.2 MCLK Factor
      • 9.2.7.3 Output Fs
      • 9.2.7.4 Decoder and Decoder Mode
      • 9.2.7.5 MPM and MPM Mode
      • 9.2.7.6 VPM and VPM Mode
      • 9.2.7.7 PPM
      • 9.2.7.8 PPM Mode List
      • 9.2.7.9 Refresh Button
      • 9.2.7.10 Apply Button
• Appendix A FAQ
  • A.1 Introduction
  • A.2 List of Questions and Answers
• Appendix B Optional Features
  • B.1 Introduction
  • B.2 Communication Using the Parallel Control Port
• Appendix C Loading/Unloading Firmware Modules
  • C.1 Introduction
    • C.1.1 DTS 96/24™ and DTS-ES™
      • C.1.1.1 Loading DTS 96/24 Decoder
      • C.1.1.2 Switching to DTS-ES from DTS 96/24 Decoder
    • C.1.2 DTS-ES Matrix and DTS Neo6™
      • C.1.2.1 Loading DTS-ES Decoder in Matrix Mode
    • C.1.3 Dolby Digital®
      • C.1.3.1 Loading Dolby Digital Decoder for Stereo Output
      • C.1.3.2 Setting Dolby Digital to AC3 DRC Mode
    • C.1.4 Cirrus Logic Signal Generator (SGEN)
      • C.1.4.1 Loading the Cirrus Logic SGEN Module
    • C.1.5 Dolby Digital®PLus
      • C.1.5.1 Loading Dolby Digital Plus for Stereo Output
      • C.1.5.2 Setting DRC Modes for Dolby Digial Plus
    • C.1.6 Dolby® TrueHD
      • C.1.6.1 Loading Dolby TrueHD for Stereo Downmix Output
      • C.1.6.2 Setting DRC Modes for Dolby TrueHD
    • C.1.7 Dolby ProLogic® IIx
      • C.1.7.1 Loading Dolby ProLogic IIx
      • C.1.7.2 Using Dolby ProLogic IIx to Output HD Audio Streams
    • C.1.8 Dolby Virtual Speaker® 2
      • C.1.8.1 Loading Dolby Virtual Speaker 2
      • C.1.8.2 Loading Dolby Virtual Speaker 2 with Dolby ProLogic II
      • C.1.8.3 Removing Dolby Virtual Speaker 2
    • C.1.9 Dolby Headphone® 2
      • C.1.9.1 Loading Dolby Headphone 2
      • C.1.9.2 Loading Dolby Headphone 2 with Dolby ProLogic II
      • C.1.9.3 Removing Dolby Headphone 2
    • C.1.10 DTS-HD™ High Resolution Audio
      • C.1.10.1 Loading DTS-HD High Resolution Audio for Stereo Downmix Output
    • C.1.11 DTS-HD™ Master Audio
      • C.1.11.1 Loading DTS-HD Master Audio for Stereo Downmix Output
    • C.1.12 Crossbar (Downmix and Upmix)
      • C.1.12.1 Loading Crossbar with Legacy and PCM Modules
      • C.1.12.2 Loading Crossbar for Dual Zone Output with Logic 7 and HD Decoders
    • C.1.13 Intelligent Room Calibration 2 (IRC2)
      • C.1.13.1 Configuring the DSP for IRC2
• Revision History