ADLINK PCIe-7350 - Manual (Page 16)

6 Introduction
Figure 1-1: Acquisition Timing Diagram
DI Sampled Clock
(AFI7)
t
AF7D
= Time delay of external sampled clock from AFI7 to internal
t
DID
= Time delay of DI data from VHDCI connector to internal
D0 D1 D2 D3
t
AF7D
Trace & component delay
D0 D1 D2 D3
t
DID
DI Data
(connector)
DI Sampled Clock
(into FPGA)
DI Data
(into FPGA)
t
SU
t
H