ADLINK PCIe-7350 - Manual (Page 17)

Introduction 7
Figure 1-2: Generation Timing Diagram
D0
DO Sampled Clock
(internal)
DO Data
Write data to
external device
t
SC2AF6
= Time delay from sampled clock (internal) to exported sampled clock (AFI6)
t
AF62D
= Time delay from exported sampled clock (AFI6) to do data
Exported DO Sampled Clock
(AFI6/ non-inverted)
t
SC2AF6
Exported DO Sampled Clock
(AFI6/ inverted)
Exported DO Sampled Clock
(AFI6/ phase delay)
Phase delay
(0° ~ 360°)
D1 D2
t
AF62D
Gerenation start
t
ECskew
t
ECskew
= Time delay from exported clock (AFI6) to exported clock (SMB CLK out)
Exported DO Sampled Clock
(SMB CLK out/ non-inverted)
Trace & component delay