ADLINK PCIe-7350 - Manual (Page 42)

32 Function Block and Operation Theory
3.6.2 Digital Output (DO) Sample Clock
For the operation of digital pattern generation in continuous mode
or burst handshaking mode, PCIe-7350 card can generate digital
data to external devices at a specific update rate (DO sample
clock). DO sample clock can be selected as the following two
clock sources:

Internal DO sample clock – the PCIe-7350 can internally
generate the sample clock signal for digital data generation.
With an internal clock source of 100MHz, the PCIe-7350
can generate any clock frequency of 100 MHz/n, where n is
any integer from 2 to 65535.

External DO sample clock – the PCIe-7350 can receive an
external sample clock signal from AFI6 or SMB CLK con-
nector as the DO sample clock for synchronization applica-
tions.
In addition, the PCIe-7350 can also export DO sample clock to
external devices through AFI6 pin or SMB CLK connector. Figure
3-8 shows the DI/DO sample clock architecture of PCIe-7350.