ADLINK PCIe-7350 - Manual (Page 44)

34 Function Block and Operation Theory
DI Sample CLK DO Sample CLK
Internal
clock
Source
On-board 100 MHz
oscillator On-board 100 MHz
oscillator
Freq.
100 MHz/n 
(n = 2~65535)
100 MHz/n 
(n = 2~ 65535)
External
clock
Source
AFI7 
SMB CLK in
AFI6 
SMB CLK in
Freq. 0 – 100 MHz 0 – 100 MHz
Freq.
(phase shift)
2 MHz – 50 MHz 2 MHz – 50 MHz
Sample
clock
exporting
Destination
AFI7 
SMB CLK out
AFI6 
SMB CLK out
Freq. 0 – 50 MHz 0 – 50 MHz
Freq.
(phase shift)
2 MHz – 50 MHz 2 MHz – 50 MHz
Table 3-4: DI/DO Sample Clock Configuration of the PCIe-7350