ADLINK PCIe-7350 - Manual (Page 43)

Function Block and Operation Theory 33
Figure 3-9: DI/DO Sample Clock Architecture
16 steps
phase shift
I
AFI7
1/N
DI C
LK
Mux
Int. DI sampled clk
16 steps
phase shift
DI Sampled CLK
Acquisition
Engine
Int. Timebase
Ext. DI sampled clk
SMB CLK out
I
AFI6
E
xt.
D
O
C
L
K
Mu
x
Ex
t. DI
CL
K
Mu
x
E
xpo
rt
. D
I/D
O
C
LK
Mu
x
Ex
port. D
I C
L
K
Mu
x
16 steps
phase shift
AFI6
O
Ex
port. D
O
C
LK
Mu
x
DO sampled clk
SMB CLK in
DO
C
LK
Mux
16 steps
phase shift
Int. DO sampled clk
1/N
DO Sampled CLK
Gereration
Engine
Ext. DO sampled clk
O
AFI7
100MHz
DI sampled clk