ADLINK PCIe-7350 - Manual (Page 59)

Function Block and Operation Theory 49
Step1: Configuration

Define DO port configuration (32/24/16/8-bits data width)

Define DO logic level configuration (3.3/2.5/1.8 V)
 Define DO sample clock configuration (internal/external)
 If choose internal sampled clock, you can define sam-
pling clock rate to be 100 MHz/n (n = 2-65535)

If choose external sampled clock, the phase shift func-
tion is available when external clock rate is from 2 MHz -
50 MHz.
 Define DO exporting sample clock configuration (AFI6/SMB
CLK out)

The PCIe-7350 can also export DO sampled clock to
external devices. The destination of the exported DO
sampled clock can be AFI6 or SMB CLK out connector.

The phase shift function is available when exported
clock rate is from 2 MHz – 50 MHz.
 Define DO-REQ and DO-ACK signal (AFI0 - AFI7)
 For example: if configure AFI3 as DO-REQ and AFI4 as
DO-ACK, and then you must connect the handshaking
signal (DO-REQ and DO-ACK) of external device to the
AFI3 and AFI4.
 Define DO starting mode configuration (NoWait or Wait-
TRIG)

If choose WaitTRIG, you can define start trigger source
to be software trigger or external trigger (DO-Start or
DO-TRIG) from AFI0 - AFI7.
 Define DO data count