ADLINK PCIe-7350 - Manual (Page 39)

Function Block and Operation Theory 29
3.5 Bus-mastering DMA Data Transfer
Digital I/O data transfer between PCIe-7350 and PC’s system
memory is through bus mastering DMA, which is controlled by
PCIe IP Core.
Figure 3-7: Maximum Data Throughput of the PCIe-7350
The bus-mastering controller controls the PCI/PCIe bus when it
becomes the master of the bus. Bus mastering reduces the size of
the on-board memory and reduces the CPU loading because data
is directly transferred to the computer’s memory without host CPU
intervention.
Bus-mastering DMA provides the fastest data transfer rate on PCI-
bus. Once the analog/digital input operation starts, control returns
to your program. The hardware temporarily stores the acquired
data in the on-board Data FIFO and then transfers the data to a
user-defined DMA buffer memory in the computer. Please note
that even when the acquired data length is less than the Data
FIFO, the data will not be kept in the Data FIFO but directly trans-
ferred into host memory by the bus-mastering DMA.
The DMA transfer mode is very complex to program. We recom-
mend using a high-level program library provided by our driver to
configure this card. By using a high-level programming library for
high speed DMA data acquisition, users simply need to assign the
sampling period and the number of conversion into their specified
counters. After the trigger condition is matched, the data will be
transferred to the system memory by the bus-mastering DMA.
The PCI/PCIe controller also supports the function of scatter/
gather bus mastering DMA, which helps the users to transfer large
amounts of data by linking all the memory blocks into a continuous
linked list.
System
Memory
NB
Chipset
120MB/s 250MB/s
PC Main-board
PCI-Express
IP Core
8K
FIFO
500MB/s 200MB/s
DUT
PCIe-7350