ADLINK PCIe-7350 - Manual (Page 34)

24 Function Block and Operation Theory
Figure 3-2: DI Row Data Mapping for 8 Bits Data Width
CH7 ~ CH0
(sample #1)
CH7 ~ CH0
(sample #2)
CH7 ~ CH0
(sample #3)
CH7 ~ CH0
(sample #4)
CH15 ~ CH8
(sample #1)
CH15 ~ CH8
(sample #2)
CH15 ~ CH8
(sample #3)
CH15 ~ CH8
(sample #4)
CH23 ~ CH16
(sample #1)
CH23 ~ CH16
(sample #2)
CH23 ~ CH16
(sample #3)
CH23 ~ CH16
(sample #4)
CH31 ~ CH24
(sample #1)
CH31 ~ CH24
(sample #2)
CH31 ~ CH24
(sample #3)
CH31 ~ CH24
(sample #4)
Configured
input ports
A B C D
A B C D
A B C D
A B C D
Configured
input ports
Configured
input ports
Configured
input ports