ADLINK PCIe-7350 - Manual (Page 48)

38 Function Block and Operation Theory
3.7.3 DO DMA in Continuous Mode
For the DO pattern generation operation in continuous mode,
PCIe-7350 card can generate digital data to external devices at a
specific update clock rate (DO sample clock). DO sample clock
can be selected from internal or external clock source. The opera-
tion sequences are listed as follows:
Steps:

Define DO port configuration (32/24/16/8-bits data width)

Define DO logic level configuration (3.3/2.5/1.8 V)

Define DO sample clock configuration (internal/external)

If choose internal sample clock, you can define sampling
clock rate to be 100MHz/n (n = 2~65535)

If choose external sample clock, the phase shift function
is available when external clock rate is 2MHz ~ 50MHz.

Define DO exporting sample clock configuration (AFI6/SMB
CLK out)

PCIe-7350 can also export DO sample clock to external
devices. The destination of DO sample clock exporting
can be AFI6 or SMB CLK out connector.
 The phase shift function is available when exported
clock is a free-running clock and the clock rate is 2MHz ~
50MHz.

Define DO starting mode configuration (NoWait or Wait-
TRIG)
 If choose WaitTRIG, you can define start trigger source
to be software trigger or external trigger (DO-Start) from
AFI0 ~ AFI7.

Define DO data count.

Execute DO DMA Write Command (continuous mode)