ADLINK PCIe-7350 - Manual (Page 36)

26 Function Block and Operation Theory
Figure 3-4: DI Row Data Mapping for 24 bits Data Width
Figure 3-5: DI Row Data Mapping for 32 Bits Data Width
CH23 ~ CH0
(sample #1)
CH7 ~ CH0
(sample #2)
CH15 ~ CH0 CH31 ~ CH24 CH7 ~ CH0
(sample #2)
CH7 ~ CH0 CH7 ~ CH0
(sample #2)
CH15 ~ CH8
(sample #2)
Configured
input ports
A B C D
A B C D
A B C D
A B C D
Configured
input ports
Configured
input ports
Configured
input ports
(sample #1)
CH31 ~ CH16
(sample #1)
CH31 ~ CH8
(sample #1)
A B C D
Configured
input ports
CH31 ~ CH0
(sample #1)