ADLINK PCIe-7350 - Manual (Page 50)

40 Function Block and Operation Theory
The timing diagram of DO DMA in continuous mode is shown as
below:
Figure 3-13: DO Timing Diagram
D0 D1 D2
DO Sampled Clock
Start Trigger
(DO-Start)
DO Data
Write data to
external device
Wait for
start trigger
t
W
t
W
= Minimum detectable trigger width
D3 D4
t
ET2D
t
ET2D
= Delay from external trigger to do data out (about 5 cycle)
Exported DO Sampled Clock
(falling edge)
Software Trigger out
(DO-SW)
t
IT2D
t
IT2D = Delay from software trigger out to do data out (about 4 cycle)