ADLINK PCIe-7350 - Manual (Page 18)

8 Introduction
External Clock I/O Specification
CLK IN (SMB Jack Connector)
Destination DI or DO sample clock
Input coupling AC
Input Impedance 50 Ω
Minimum detectable pulse width 8 ns
External sampled clock range
Square Wave
Voltage 0.2 Vpp to 5 Vpp
Frequency 100 KHz - 50 MHz
Duty cycle 40% - 60%
Sine Wave
Voltage 0.2 Vpp to 5 Vpp
Frequency 100 KHz – 50 MHz
CLK OUT (SMB Jack Connector)
Sources DI or DO sample clock
Source impedance 50 Ω
Logic Levels

(programmable)
The same logic level of AFI I/O
(1.8 V, 2.5 V, or 3.3 V)
Driving Capacity (Max.)
±8 mA at 1.8 V
±16 mA at 2.5 V
±32 mA at 3.3 V
I
2
C Master Specification
Signal
Direction Pin
SCL O AFI0
SDA I/O AFI1
Supported clock rate

(programmable)
1.9 kHz -244.14 kHz;
488.28125 kHz / (n + 1); 1 ≤ n ≤ 255
Transfer size of Data 0 - 4 Bytes
Transfer size of Cmd/ Addr 0 - 4 Bytes
Logic families

(programmable)
1.8 V 2.5 V 3.3 V
Input Voltage
Min. V
IH
1.2 V 1.6 V 2.0 V
Max. V
IL
0.63 V 0.7 V 0.8 V
Output Voltage
Min. V
OH
1.6 V 2.3 V 3.1 V
Max. V
OL
0.2 V 0.2 V 0.2 V