ADLINK PCIe-7350 - Manual (Page 41)

Function Block and Operation Theory 31
3.6 Sample Clock
The sample clock controls the data rate of digital pattern acquisi-
tion and generation. For PCIe-7350, the sample clock can be con-
figured from internal timer pacer or external clock through the
SMB connectors or SCSI-VHDCI connector.
3.6.1 Digital Input (DI) Sample Clock
For the operation of digital pattern acquisition in continuous mode
or burst handshaking mode, the PCIe-7350 card can acquire digi-
tal data from external devices at a specific sampling rate (DI sam-
ple clock). DI sample clock can be selected as the following two
clock sources:

Internal DI sample clock – the PCIe-7350 can internally
generate the sample clock signal for digital data acquisition.
With an internal base clock source of 100 MHz, the PCIe-
7350 can generate any clock frequency of 100 MHz/n,
where n is any integer from 2 to 65535.

External DI sample clock – the PCIe-7350 can receive
external clock signal from AFI7 or SMB CLK as the DI sam-
ple clock for synchronization applications.
In addition, the PCIe-7350 can also export DI sample clock to
external devices through AFI7 pin or SMB CLK connector.