ADLINK PCIe-7350 - Manual (Page 8)

iv List of Figures
List of Figures
Figure 1-1: Acquisition Timing Diagram ....................................... 6
Figure 1-2: Generation Timing Diagram....................................... 7
Figure 2-1: PCB Layout and Mechanical Drawing
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of the PCIe-7350 ..................................................... 11
Figure 3-1: PCIe-7350 Block Diagram ....................................... 20
Figure 3-2: DI Row Data Mapping for 8 Bits Data Width............ 24
Figure 3-3: DI Row Data Mapping for 16 Bits Data Width.......... 25
Figure 3-4: DI Row Data Mapping for 24 bits Data Width .......... 26
Figure 3-5: DI Row Data Mapping for 32 Bits Data Width.......... 26
Figure 3-6: Phase Shift of Sample Clock ................................... 27
Figure 3-7: Maximum Data Throughput of the PCIe-7350 ......... 29
Figure 3-8: Scatter-Gather DMA for Data Transfer .................... 30
Figure 3-9: DI/DO Sample Clock Architecture ........................... 33
Figure 3-10: DI Continuous Mode Architecture............................ 36
Figure 3-11: DI Timing Diagram................................................... 37
Figure 3-12: DO Continuous Mode Architecture .......................... 39
Figure 3-13: DO Timing Diagram ................................................. 40
Figure 3-14: DI Handshaking Mode Architecture ......................... 42
Figure 3-15: DI Handshaking Timing Diagram............................. 43
Figure 3-16: DO Handshaking Mode Architecture ....................... 45
Figure 3-17: DO Handshaking Timing Diagram ........................... 45
Figure 3-18: DI Burst Handshaking Mode Architecture................ 47
Figure 3-19: DI Burst Handshaking Timing Diagram ................... 48
Figure 3-20: DO Burst Handshaking Mode Architecture.............. 50
Figure 3-21: DO Burst Handshaking Timing Diagram.................. 51
Figure 3-22: DI Post Trigger......................................................... 52
Figure 3-23: DO Post Trigger....................................................... 53
Figure 3-24: DI Post Trigger with Re-trigger ................................ 53
Figure 3-25: DO Post Trigger with Re-Trigger ............................. 54
Figure 3-26: DI Gated Trigger ...................................................... 54
Figure 3-27: DO Gated Trigger .................................................... 55
Figure 3-28: I2C Master of PCIe-7350 ......................................... 60
Figure 3-29: Data Transfer on the I2C Bus .................................. 60
Figure 3-30: I2C Data Format ...................................................... 61
Figure 3-31: SPI Master of PCIe-7350......................................... 62
Figure 3-32: Data Transfer on SPI Bus........................................ 63
Figure 3-33: Clock Mode of SCK ................................................. 63
Figure 3-34: External Digital Trigger Input Configuration............. 64