ADLINK PCIe-7350 - Manual (Page 73)

Function Block and Operation Theory 63
SPI master of PCIe-7350 provide at most 64 bits -- 32 bits
address/ command and 32 bits data. SPI master of PCIe-7350
supports only three slave devices. Figure 3-32 shows the data
transfer on SPI bus.
Figure 3-32: Data Transfer on SPI Bus
SPI master of PCIe-7350 supports clock frequency range from
244.14 kHz to 62.5 MHz. After issuing command to SPI slave
device, the clock rate might be changed according the request
from SPI slave. The below formula is to calculate the SPI clock
rate.
Fscl = 62.5 / (Clk Pre-scale + 1) (MHz), 
where Clk Pre-scale=0~255
SPI master of PCIe-7350 supports two different modes of SCK.
Figure 3-11 shows the clock mode 0 and clock mode 1 of SCK.
Figure 3-33: Clock Mode of SCK
CS#
SCK
Data
Data
SDO
SDI
Cmd/Addr
Cmd/Addr 0 ~ 32b
RD 0 ~ 32b
TD 0 ~ 32b dummy dummy
dummy
CS#
SCK
Mode =1
Mode =0