Altera Arria V SoC Development Board - Manual (Page 13)

Chapter 2: Board Components 2–5
Featured Device: Arria V SoC
July 2014 Altera Corporation Arria V SoC Development Board
Reference Manual
Featured Device: Arria V SoC
The Arria V SoC development board features a Arria V SoC 5ASTFD5K3F40I3 device
(U41) that includes a hard processor system (HPS) with integrated ARM
® Cortex ® -A9
MPCore processor.
f
For more information about Arria V device family, refer to the Arria V Device
Handbook .
Table 2–2 describes the features of the Arria V SoC device.
I/O Resources
The Arria V SoC 5ASTFD5K3F40I3 device has 540 general purpose FPGA I/O pins
and 210 general purpose HPS I/O pins.
MAX V CPLD 5M2210 System Controller
The board utilizes the 5M2210ZF256 System Controller, an Altera MAX V CPLD, for
the following purposes:
■ FPGA configuration from flash
■ Power measurement
■ Control and status registers (CSR) for remote system update
Table 2–2. Arria V SoC Features
Resource 5ASTFD5K3F40I3
LE (K) 462
ALM 174,340
Register 697,360
Memory (Kb)
M10K 22,820
MLAB 2,658
18-bit × 18-bit Multiplier 2,180
PLLs
FPGA 14
HPS 3
Transceivers
6 Gbps 30
10 Gbps 16