Altera Arria V SoC Development Board - Manual (Page 55)

Chapter 2: Board Components 2–47
Memory
July 2014 Altera Corporation Arria V SoC Development Board
Reference Manual
DDR3 x16 (U44)
N3 DDR3_HPS_A0 N9 1.5-V SSTL Class I Address bus
P7 DDR3_HPS_A1 M9 1.5-V SSTL Class I Address bus
P3 DDR3_HPS_A2 N10 1.5-V SSTL Class I Address bus
N2 DDR3_HPS_A3 M10 1.5-V SSTL Class I Address bus
P8 DDR3_HPS_A4 A8 1.5-V SSTL Class I Address bus
P2 DDR3_HPS_A5 B7 1.5-V SSTL Class I Address bus
R8 DDR3_HPS_A6 B9 1.5-V SSTL Class I Address bus
R2 DDR3_HPS_A7 A9 1.5-V SSTL Class I Address bus
T8 DDR3_HPS_A8 D9 1.5-V SSTL Class I Address bus
R3 DDR3_HPS_A9 C10 1.5-V SSTL Class I Address bus
L7 DDR3_HPS_A10 K7 1.5-V SSTL Class I Address bus
R7 DDR3_HPS_A11 J7 1.5-V SSTL Class I Address bus
N7 DDR3_HPS_A12 F9 1.5-V SSTL Class I Address bus
T3 DDR3_HPS_A13 E9 1.5-V SSTL Class I Address bus
T7 DDR3_HPS_A14 D11 1.5-V SSTL Class I Address bus
M2 DDR3_HPS_BA0 L7 1.5-V SSTL Class I Bank address bus
N8 DDR3_HPS_BA1 C9 1.5-V SSTL Class I Bank address bus
M3 DDR3_HPS_BA2 D8 1.5-V SSTL Class I Bank address bus
K3 DDR3_HPS_CASN G9 1.5-V SSTL Class I Row address select
K9 DDR3_HPS_CKE R8 1.5-V SSTL Class I Column address select
J7 DDR3_HPS_CLK_P A11 1.5-V SSTL Class I Differential output clock
K7 DDR3_HPS_CLK_N B10 1.5-V SSTL Class I Differential output clock
L2 DDR3_HPS_CSN H9 1.5-V SSTL Class I Chip select
E7 DDR3_HPS_DM2 D3 1.5-V SSTL Class I Write mask byte lane
D3 DDR3_HPS_DM3 D1 1.5-V SSTL Class I Write mask byte lane
F2 DDR3_HPS_DQ16 J5 1.5-V SSTL Class I Data bus
H3 DDR3_HPS_DQ17 K5 1.5-V SSTL Class I Data bus
G2 DDR3_HPS_DQ18 N7 1.5-V SSTL Class I Data bus
F8 DDR3_HPS_DQ19 F3 1.5-V SSTL Class I Data bus
H7 DDR3_HPS_DQ20 H3 1.5-V SSTL Class I Data bus
E3 DDR3_HPS_DQ21 J4 1.5-V SSTL Class I Data bus
H8 DDR3_HPS_DQ22 M5 1.5-V SSTL Class I Data bus
F7 DDR3_HPS_DQ23 C3 1.5-V SSTL Class I Data bus
A3 DDR3_HPS_DQ24 A2 1.5-V SSTL Class I Data bus
C3 DDR3_HPS_DQ25 A3 1.5-V SSTL Class I Data bus
C8 DDR3_HPS_DQ26 P7 1.5-V SSTL Class I Data bus
A7 DDR3_HPS_DQ27 C1 1.5-V SSTL Class I Data bus
Table 2–28. DDR3 SDRAM Pin Assignments, Schematic Signal Names, and Functions (Part 3 of 5)
Board
Reference
Schematic
Signal Name
Arria V SoC Pin
Number
I/O Standard Description