Altera Arria V SoC Development Board - Manual (Page 52)

2–44 Chapter 2: Board Components
Memory
Arria V SoC Development Board July 2014 Altera Corporation
Reference Manual
T2 DDR3B_RESETN AN15 1.5-V SSTL Class I Reset
L3 DDR3B_WEN AP18 1.5-V SSTL Class I Write enable
L8 DDR3B_ZQ1 — 1.5-V SSTL Class I ZQ impedance calibration
DDR3 x16 (U43)
N3 DDR3B_A0 AP16 1.5-V SSTL Class I Address bus
P7 DDR3B_A1 AN16 1.5-V SSTL Class I Address bus
P3 DDR3B_A2 AK16 1.5-V SSTL Class I Address bus
N2 DDR3B_A3 AJ16 1.5-V SSTL Class I Address bus
P8 DDR3B_A4 AV16 1.5-V SSTL Class I Address bus
P2 DDR3B_A5 AU16 1.5-V SSTL Class I Address bus
R8 DDR3B_A6 AT16 1.5-V SSTL Class I Address bus
R2 DDR3B_A7 AR16 1.5-V SSTL Class I Address bus
T8 DDR3B_A8 AP17 1.5-V SSTL Class I Address bus
R3 DDR3B_A9 AN17 1.5-V SSTL Class I Address bus
L7 DDR3B_A10 AH17 1.5-V SSTL Class I Address bus
R7 DDR3B_A11 AG17 1.5-V SSTL Class I Address bus
N7 DDR3B_A12 AM18 1.5-V SSTL Class I Address bus
T3 DDR3B_A13 AL18 1.5-V SSTL Class I Address bus
T7 DDR3B_A14 AG18 1.5-V SSTL Class I Address bus
M2 DDR3B_BA0 AE18 1.5-V SSTL Class I Bank address bus
N8 DDR3B_BA1 AD18 1.5-V SSTL Class I Bank address bus
M3 DDR3B_BA2 AC18 1.5-V SSTL Class I Bank address bus
K3 DDR3B_CASN AR18 1.5-V SSTL Class I Row address select
K9 DDR3B_CKE AM16 1.5-V SSTL Class I Column address select
J7 DDR3B_CLK_P AF16 1.5-V SSTL Class I Differential output clock
K7 DDR3B_CLK_N AE17 1.5-V SSTL Class I Differential output clock
L2 DDR3B_CSN AL17 1.5-V SSTL Class I Chip select
E7 DDR3B_DM0 AD16 1.5-V SSTL Class I Write mask byte lane
D3 DDR3B_DM1 AU13 1.5-V SSTL Class I Write mask byte lane
H8 DDR3B_DQ0 AU15 1.5-V SSTL Class I Data bus
F8 DDR3B_DQ1 AT15 1.5-V SSTL Class I Data bus
H3 DDR3B_DQ2 AH15 1.5-V SSTL Class I Data bus
H7 DDR3B_DQ3 AW13 1.5-V SSTL Class I Data bus
G2 DDR3B_DQ4 AV13 1.5-V SSTL Class I Data bus
F2 DDR3B_DQ5 AL15 1.5-V SSTL Class I Data bus
F7 DDR3B_DQ6 AW15 1.5-V SSTL Class I Data bus
E3 DDR3B_DQ7 AW14 1.5-V SSTL Class I Data bus
B8 DDR3B_DQ8 AE15 1.5-V SSTL Class I Data bus
Table 2–27. DDR3 SDRAM Pin Assignments, Schematic Signal Names, and Functions (Part 6 of 7)
Board
Reference
Schematic
Signal Name
Arria V SoC Pin
Number
I/O Standard Description