Altera Arria V SoC Development Board - Manual (Page 51)

Chapter 2: Board Components 2–43
Memory
July 2014 Altera Corporation Arria V SoC Development Board
Reference Manual
T3 DDR3B_A13 AL18 1.5-V SSTL Class I Address bus
T7 DDR3B_A14 AG18 1.5-V SSTL Class I Address bus
M2 DDR3B_BA0 AE18 1.5-V SSTL Class I Bank address bus
N8 DDR3B_BA1 AD18 1.5-V SSTL Class I Bank address bus
M3 DDR3B_BA2 AC18 1.5-V SSTL Class I Bank address bus
K3 DDR3B_CASN AR18 1.5-V SSTL Class I Row address select
K9 DDR3B_CKE AM16 1.5-V SSTL Class I Column address select
J7 DDR3B_CLK_P AF16
Differential 1.5-V
SSTL Class I
Differential output clock
K7 DDR3B_CLK_N AE17
Differential 1.5-V
SSTL Class I
Differential output clock
L2 DDR3B_CSN AL17 1.5-V SSTL Class I Chip select
E7 DDR3B_DM2 AU12 1.5-V SSTL Class I Write mask byte lane
D3 DDR3B_DM3 AV10 1.5-V SSTL Class I Write mask byte lane
H3 DDR3B_DQ16 AJ13 1.5-V SSTL Class I Data bus
F2 DDR3B_DQ17 AH13 1.5-V SSTL Class I Data bus
E3 DDR3B_DQ18 AP12 1.5-V SSTL Class I Data bus
F8 DDR3B_DQ19 AW11 1.5-V SSTL Class I Data bus
F7 DDR3B_DQ20 AW10 1.5-V SSTL Class I Data bus
H8 DDR3B_DQ21 AM13 1.5-V SSTL Class I Data bus
G2 DDR3B_DQ22 AE13 1.5-V SSTL Class I Data bus
H7 DDR3B_DQ23 AE14 1.5-V SSTL Class I Data bus
C8 DDR3B_DQ24 AW9 1.5-V SSTL Class I Data bus
B8 DDR3B_DQ25 AV9 1.5-V SSTL Class I Data bus
A7 DDR3B_DQ26 AP11 1.5-V SSTL Class I Data bus
C2 DDR3B_DQ27 AD13 1.5-V SSTL Class I Data bus
A2 DDR3B_DQ28 AC13 1.5-V SSTL Class I Data bus
D7 DDR3B_DQ29 AL12 1.5-V SSTL Class I Data bus
C3 DDR3B_DQ30 AG13 1.5-V SSTL Class I Data bus
A3 DDR3B_DQ31 AF13 1.5-V SSTL Class I Data bus
F3 DDR3B_DQS_P2 AW12
Differential 1.5-V
SSTL Class I
Data strobe P byte lane 2
G3 DDR3B_DQS_N2 AV12
Differential 1.5-V
SSTL Class I
Data strobe N byte lane 2
C7 DDR3B_DQS_P3 AU11
Differential 1.5-V
SSTL Class I
Data strobe P byte lane 3
B7 DDR3B_DQS_N3 AT11
Differential 1.5-V
SSTL Class I
Data strobe N byte lane 3
K1 DDR3B_ODT AD19 1.5-V SSTL Class I On-die termination enable
J3 DDR3B_RASN AD17 1.5-V SSTL Class I Row address select
Table 2–27. DDR3 SDRAM Pin Assignments, Schematic Signal Names, and Functions (Part 5 of 7)
Board
Reference
Schematic
Signal Name
Arria V SoC Pin
Number
I/O Standard Description