Altera Arria V SoC Development Board - Manual (Page 57)

Chapter 2: Board Components 2–49
Memory
July 2014 Altera Corporation Arria V SoC Development Board
Reference Manual
K7 DDR3_HPS_CLK_N B10 1.5-V SSTL Class I Differential output clock
L2 DDR3_HPS_CSN H9 1.5-V SSTL Class I Chip select
E7 DDR3_HPS_DM0 C6 1.5-V SSTL Class I Write mask byte lane
D3 DDR3_HPS_DM1 E4 1.5-V SSTL Class I Write mask byte lane
F7 DDR3_HPS_DQ0 D7 1.5-V SSTL Class I Data bus
F8 DDR3_HPS_DQ1 C7 1.5-V SSTL Class I Data bus
F2 DDR3_HPS_DQ2 R10 1.5-V SSTL Class I Data bus
E3 DDR3_HPS_DQ3 G7 1.5-V SSTL Class I Data bus
H8 DDR3_HPS_DQ4 A6 1.5-V SSTL Class I Data bus
H3 DDR3_HPS_DQ5 A7 1.5-V SSTL Class I Data bus
G2 DDR3_HPS_DQ6 L6 1.5-V SSTL Class I Data bus
H7 DDR3_HPS_DQ7 D6 1.5-V SSTL Class I Data bus
C3 DDR3_HPS_DQ8 H6 1.5-V SSTL Class I Data bus
A3 DDR3_HPS_DQ9 G6 1.5-V SSTL Class I Data bus
A2 DDR3_HPS_DQ10 N8 1.5-V SSTL Class I Data bus
D7 DDR3_HPS_DQ11 G5 1.5-V SSTL Class I Data bus
A7 DDR3_HPS_DQ12 A4 1.5-V SSTL Class I Data bus
B8 DDR3_HPS_DQ13 A5 1.5-V SSTL Class I Data bus
C2 DDR3_HPS_DQ14 R9 1.5-V SSTL Class I Data bus
C8 DDR3_HPS_DQ15 F4 1.5-V SSTL Class I Data bus
F3 DDR3_HPS_DQS_P0 F7
Differential 1.5-V
SSTL Class I
Data strobe P byte lane 1
G3 DDR3_HPS_DQS_N0 E7
Differential 1.5-V
SSTL Class I
Data strobe P byte lane 0
C7 DDR3_HPS_DQS_P1 D5
Differential 1.5-V
SSTL Class I
Data strobe N byte lane 1
B7 DDR3_HPS_DQS_N1 E6
Differential 1.5-V
SSTL Class I
Data strobe N byte lane 0
K1 DDR3_HPS_ODT H7 1.5-V SSTL Class I On-die termination enable
J3 DDR3_HPS_RASN G8 1.5-V SSTL Class I Row address select
T2 DDR3_HPS_RESETN E3 1.5-V SSTL Class I Reset
L3 DDR3_HPS_WEN J8 1.5-V SSTL Class I Write enable
L8 DDR3_HPS_ZQ — 1.5-V SSTL Class I ZQ impedance calibration
Table 2–28. DDR3 SDRAM Pin Assignments, Schematic Signal Names, and Functions (Part 5 of 5)
Board
Reference
Schematic
Signal Name
Arria V SoC Pin
Number
I/O Standard Description