Measurement Computing USB-2527 - Manual (Page 31)

USB-2527 User's Guide Functional Details
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If no analog inputs are being scanned, the digital inputs can sustain rates up to 4 MHz. Higher rates—up to
12 MHz—are possible depending on the platform and the amount of data being transferred.
Digital outputs and pattern generation
Digital outputs can be updated asynchronously at anytime before, during, or after an acquisition. You can use
two of the 8-bit ports to generate a digital pattern at up to 4 MHz. The USB-2527 supports digital pattern
generation. The digital pattern can be read from PC RAM.
Higher rates—up to 12 MHz—are possible depending on the platform and the amount of data being transferred.
Digital pattern generation is clocked using an internal clock. The on-board programmable clock generates
updates ranging from once every 1 second to 1 MHz, independent of any acquisition rate.
Triggering
Triggering can be the most critical aspect of a data acquisition application. The USB-2527 supports the
following trigger modes to accommodate certain measurement situations.
Hardware analog triggering
The USB-2527 uses true analog triggering in which the trigger level you program sets an analog DAC, which is
then compared in hardware to the analog input level on the selected channel. This guarantees an analog trigger
latency that is less than 1 µs.
You can select any analog channel as the trigger channel, but the selected channel must be the first channel in
the scan. You can program the trigger level, the rising or falling edge, and hysteresis.
A note on the hardware analog level trigger and comparator change state
When analog input voltage starts near the trigger level, and you are performing a rising or falling hardware
analog level trigger, the analog level comparator may have already tripped before the sweep was enabled. If this
is the case, the circuit waits for the comparator to change state. However, since the comparator has already
changed state, the circuit does not see the transition.
To resolve this problem, do the following:
1. Set the analog level trigger to the threshold you want.
2. Apply an analog input signal that is more than 2.5% of the full-scale range away from the desired
threshold. This ensures that the comparator is in the proper state at the beginning of the acquisition.
3. Bring the analog input signal toward the desired threshold. When the input signal is at the threshold
(± some tolerance) the sweep will be triggered.
4. Before re-arming the trigger, move the analog input signal to a level that is more than 2.5% of the full-scale
range away from the desired threshold.
For example, if you are using the ±2 V full-scale range (gain = 5), and you want to trigger at +1 V on the rising
edge, you would set the analog input voltage to a start value that is less than +0.9 V (1 V – (2 V * 2 * 2.5%)).
Digital triggering
A separate digital trigger input line is provided (TTL TRG), allowing TTL-level triggering with latencies
guaranteed to be less than 1 µs. You can program both of the logic levels (1 or 0) and the rising or falling edge
for the discrete digital trigger input.