Samsung S3F80JB - Manual (Page 257)

TIMER 1 S3F80JB
11-2
TIMER 1 OVERFLOW INTERRUPT
Timer 1 can be programmed to generate an overflow interrupt (IRQ1, F4H) whenever an overflow occurs in the
16-bit up counter. When you set the Timer 1 overflow interrupt enable bit, T1CON.2, to “1”, the overflow interrupt
is generated each time the 16-bit up counter reaches ‘FFFFH’. After the interrupt request is generated, the
counter value is automatically cleared to ‘00H’ and up counting resumes. By writing a “1” to T1CON.3, you can
clear/reset the 16-bit counter value at any time during program operation.
TIMER 1 CAPTURE INTERRUPT
Timer 1 can be used to generate a capture interrupt (IRQ1, vector F6H) whenever a triggering condition is
detected at the P3.0 pin for 32 pin package and P3.3 pin for 44 pin package. The T1CON.5 and T1CON.4 bit-pair
setting is used to select the trigger condition for capture mode operation: rising edges, falling edges, or both
signal edges.
In capture mode, program software can poll the Timer 1 match/capture interrupt pending bit, T1CON.0, to detect
when a Timer 1 capture interrupt pending condition exists (T1CON.0 = “1”). When the interrupt request is
acknowledged by the CPU and the service routine starts, the interrupt service routine for vector F6H must clear
the interrupt pending condition by writing a “0” to T1CON.0.
Interrupt
Enable/Disable
(T1CON.1)
IRQ1
(T1INT)
P3.0 or P3.3
(note)
Timer 1 Data
IRQ1 (T1OVF)
16-Bit Up Counter
CLK
T1CON.5
T1CON.4
Pending
(T1CON.0)
T1CON.2
NOTE: P3.0 is assigned as T1CAP function for 32 pin package and P3.3 is assigned
as T1CAP function for 44 pin package.
Figure 11-1. Simplified Timer 1 Function Diagram: Capture Mode