Samsung S3F80JB - Manual (Page 96)

S3F80JB CONTROL REGISTERS
4-29
P2PND
— Port 2 External Interrupt Pending Register E6H Set1 Bank0
Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0
Reset Value 0 0 0 0 0 0 0 0
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Addressing Mode Register addressing mode only
.7 P2.7 External Interrupt (INT9) Pending Flag Bit (see Note)
0 No P2.7 external interrupt pending (when read)
1 P2.7 external interrupt is pending (when read)
.6
P2.6 External Interrupt (INT9) Pending Flag Bit
0 No P2.6 external interrupt pending (when read)
1 P2.6 external interrupt is pending (when read)
.5
P2.5 External Interrupt (INT9) Pending Flag Bit
0 No P2.5 external interrupt pending (when read)
1 P2.5 external interrupt is pending (when read)
.4
P2.4 External Interrupt (INT9) Pending Flag Bit
0 No P2.4 external interrupt pending (when read)
1 P2.4 external interrupt is pending (when read)
.3
P2.3 External Interrupt (INT8) Pending Flag Bit
0 No P2.3 external interrupt pending (when read)
1 P2.3 external interrupt is pending (when read)
.2
P2.2 External Interrupt (INT7) Pending Flag Bit
0 No P2.2 external interrupt pending (when read)
1 P2.2 external interrupt is pending (when read)
.1
P2.1 External Interrupt (INT6) Pending Flag Bit
0 No P2.1 external interrupt pending (when read)
1 P2.1 external interrupt is pending (when read)
.0
P2.0 External Interrupt (INT5) Pending Flag Bit
0 No P2.0 external interrupt pending (when read)
1 P2.0 external interrupt is pending (when read)
NOTE: To clear an interrupt pending condition, write a “0” to the appropriate pending flag bit. Writing a “1” to an interrupt
rending flag (P2PND.0–7) has no effect.