Samsung S3F80JB - Manual (Page 310)

ELECTRICAL DATA (4MHz) S3F80JB
17-10
t INTH t INTL
0.8 V DD
0.2 V DD 0.2 V DD
0.8 V DD
NOTE: The unit t CPU means one CPU clock period.
Figure 17-10. Input Timing for External Interrupts (Port 0 and Port 2)
Normal
Operating
Mode
Oscillation Stabilization Time
Reset
Occur
V DD
NOTE: t WAIT is the same as 4096 x 16 x 1/f OSC .
t WAIT
Normal Operating Mode
Back-up Mode
(Stop Mode)
nRESET
Figure 17-11. Input Timing for Reset (nRESET Pin)