P0conh – Samsung S3F80JB User Manual
Page 86
S3F80JB
CONTROL REGISTERS
4-19
P0CONH
— Port 0 Control Register (High Byte)
E8H Set1 Bank0
Bit
Identifier
.7 .6 .5 .4 .3 .2 .1 .0
Reset Value
0 0 0 0 0 0 0 0
Read/Write
R/W R/W R/W R/W R/W R/W R/W R/W
Addressing Mode
Register addressing mode only
.7 and .6
P0.7/INT4 Mode Selection Bits
0
0
C-MOS input mode; interrupt on falling edges
0
1
C-MOS input mode; interrupt on rising and falling edges
1
0
Push-pull output mode
1
1
C-MOS input mode; interrupt on rising edges
.5 and .4
P0.6/INT4 Mode Selection Bits
0
0
C-MOS input mode; interrupt on falling edges
0
1
C-MOS input mode; interrupt on rising and falling edges
1
0
Push-pull output mode
1
1
C-MOS input mode; interrupt on rising edges
.3 and .2
P0.5/INT4 Mode Selection Bits
0
0
C-MOS input mode; interrupt on falling edges
0
1
C-MOS input mode; interrupt on rising and falling edges
1
0
Push-pull output mode
1
1
C-MOS input mode; interrupt on rising edges
.1 and .0
P0.4/INT4 Mode Selection Bits
0
0
C-MOS input mode; interrupt on falling edges
0
1
C-MOS input mode; interrupt on rising and falling edges
1
0
Push-pull output mode
1
1
C-MOS input mode; interrupt on rising edges
NOTES:
1. The INT4 external interrupts at the P0.7–P0.4 pins share the same interrupt level (IRQ7) and interrupt vector address
(E8H).
2. You can assign pull-up resistors to individual port 0 pins by making the appropriate settings to the P0PUR register.
(P0PUR.7 – P0PUR.4)