Samsung S3F80JB - Manual (Page 263)

COUNTER A S3F80JB
12-2
MUX 16-Bit Down Counter
MUX
Counter A Data
Low Byte Register
IRQ2
(CAINT)
NOTE: The value of the CADATAL register is loaded into the 8-bit counter when the
operation of the counter A stars. If a borrow occurs, the value of the
CADATAH register is loaded into the 8-bit counter. However, if the next borrow
occurs, the value of the CADATAL register is loaded into the 8-bit counter.
Data Bus
Counter A Data
High Byte Register
CACON.0
(CAOF)
Repeat
Control
CLK
DIV 1
DIV 2
DIV 4
DIV 8
CACON.2
f OSC
Interrupt
Control
CACON.4-.5
INT. GEN.
To Other Block
(P3.1/REM)
CACON.3
CACON.6-.7
Figure 12-1. Counter A Block Diagram