Rainbow Electronics 71M6542G - Manual (Page 122)

122 © 2008–2011 Teridian Semiconductor Corporation v1.1
Name Location Rst Wk Dir Description
RTM_E 2106[1] 0 0 R/W Real Time Monitor enable. When 0, the RTM output is low.
RTM0[9:8]
RTM0[7:0]
RTM1[7:0]
RTM2[7:0]
RTM3[7:0] 210D[1:0]
210E[7:0]
210F[7:0]
2110[7:0]
2111[7:0]
0
0
0
0
0 0
0
0
0
0
R/W
Four RTM probes. Before each CE code pass, the values of these registers
are serially output on the RTM pin. The RTM registers are ignored when
RTM_E = 0. Note that RTM0 is 10 bits wide. The others assume the upper
two bits are 00.
SECURE SFR B2[6] 0 0 R/W
Inhibits erasure of page 0 and flash addresses above the beginning of CE code
as defined by CE_LCTN[5:0]. Also inhibits the read of flash via the SPI and ICE
port.
SLEEP 28B2[7] 0 0 W
Puts the part to SLP mode. Ignored if system power is present. The part
wakes when the Wake timer times out, when push button is pushed, or when
system power returns.
SPI_CMD[7:0] SFR FD[7:0] – – R SPI command register for the 8-bit command from the bus master.
SPI_E 270C[4] 1 1 R/W
SPI port enable. Enables SPI interface on pins SEGDIO36 – SEGDIO39.
Requires that LCD_MAP[36-39] = 0.
SPI_SAFE 270C[3] 0 0 R/W
Limits SPI writes to SPI_CMD and a 16-byte region in DRAM. No other
writes are permitted.
SPI_STAT[7:0] 2708[7:0] 0 0 R
SPI_STAT contains the status results from the previous SPI transaction.
Bit 7: Ready error: The 71M654x was not ready to read or write as directed
by the previous command.
Bit 6: Read data parity: This bit is the parity of all bytes read from the
71M654x in the previous command. Does not include the SPI_STAT byte.
Bit 5: Write data parity: This bit is the overall parity of the bytes written to the
71M654x in the previous command. It includes CMD and ADDR bytes.
Bit 4-2: Bottom 3 bits of the byte count. Does not include ADDR and CMD
bytes. One, two, and three byte
instructions return 111.
Bit 1: SPI FLASH mode: This bit is zero when the TEST pin is zero.
Bit 0: SPI FLASH mode ready: Used in SPI FLASH mode. Indicates that the
flash is ready to receive another write instruction.
STEMP[10:3]
STEMP[2:0] 2881[7:0]
2882[7:5] –
– –
– R
R
The result of the temperature measurement.
SUM_SAMPS[12:8]
SUM_SAMPS[7:0] 2107[4:0]
2108[7:0]
0 0 R/W
The number of multiplexer cycles per XFER_BUSY interrupt. Maximum value
is 8191 cycles.
TBYTE_BUSY 28A0[3] 0 0 R
Indicates that hardware is still writing the 0x28A0 byte. Additional writes to
this byte are locked out while it is one. Write duration could be as long as
6ms.