Rainbow Electronics 71M6542G - Manual (Page 27)

v1.1 © 2008–2011 Teridian Semiconductor Corporation 27
2.3.6 Pulse Generators
The 71M6541D/F and 71M6542F provide four pulse generators, VPULSE, WPULSE, XPULSE and YPULSE,
as well as hardware support for the VPULSE and WPULSE pulse generators. The pulse generators can
be used to output CE status indicators, SAG for example, to DIO pins. All pulses can be configured to
generate interrupts to the MPU.
The polarity of the pulses may be inverted with control bit PLS_INV (I/O RAM 0x210C[0]). When this bit is
set, the pulses are active high, rather than the more usual active low. PLS_INV inverts all the pulse outputs.
The function of each pulse generator is determined by the CE code and the MPU code must configure the
corresponding pulse outputs in agreement with the CE code. For example, standard CE code produces a
mains zero-crossing pulse on XPULSE and a SAG pulse on YPULSE.
A common use of the zero-crossing pulses is to generate interrupt in order to drive real-time clock software
in places where the mains frequency is sufficiently accurate to do so and also to adjust for crystal aging.
A common use for the SAG pulse is to generate an interrupt that alerts the MPU when mains power is about
to fail, so that the MPU code can store accumulated energy and other data to EEPROM before the
V3P3SYS supply voltage actually drops.
2.3.6.1 XPULSE and YPULSE
Pulses generated by the CE may be exported to the XPULSE and YPULSE pulse output pins. Pins
SEGDIO6 and SEGDIO7 are used for these pulses, respectively. Generally, the XPULSE and YPULSE
outputs can be updated once on each pass of the CE code.
See 5.3 CE Interface Description on page 125 for details.
2.3.6.2 VPULSE and WPULSE
Referring to Figure 12 , during each CE code pass the hardware stores exported WPULSE and VPULSE sign
bits in an 8-bit FIFO and outputs them at a specified interval. This permits the CE code to calculate the
VPULSE and WPULSE outputs at the beginning of its code pass and to rely on hardware to spread them
over the multiplexer frame. As seen in
Figure 12 , the FIFO is reset at the beginning of each multiplexer
frame. As also seen in Figure 12 , the I/O RAM register PLS_INTERVAL[7:0] (I/O RAM 0x210B[7:0])
controls the delay to the first pulse update and the interval between subsequent updates. The LSB of
the PLS_INTERVAL[7:0] register is equivalent to 4 CK_FIR cycles (CK_FIR is typically 4.9152MHz if
PLL_FAST=1 and ADC_DIV=0, but other CK_FIR frequencies are possible; see the ADC_DIV definition in
Table 76 .) If PLS_INTERVAL[7:0]=0, the FIFO is deactivated and the pulse outputs are updated immediately.
The MUX frame duration in units of CK_FIR clock cycles is given by:
If PLL_FAST=1:
MUX frame duration in CK_FIR cycles = [1 + ( FIR_LEN +1) * ( ADC_DIV +1) * ( MUX_DIV )] * [150 / ( ADC_DIV +1)]
If PLL_FAST=0:
MUX frame duration in CK_FIR cycles = [3 + 3*( FIR_LEN +1) * ( ADC_DIV +1) * ( MUX_DIV )] * [48 / ( ADC_DIV +1)]
PLS_INTERVAL[7:0] in units of CK_FIR clock cycles is calculated by:
PLS_INTERVAL[7:0] = floor (Mux frame duration in CK_FIR cycles / CE pulse updates per Mux frame / 4 )
Since the FIFO resets at the beginning of each multiplexer frame, the user must specify
PLS_INTERVAL[7:0] so that all of the possible pulse updates occurring in one CE execution are output
before the multiplexer frame completes. For instance, the 71M654x CE code outputs six updates per
multiplexer interval, and if the multiplexer interval is 1950 CK_FIR clock cycles long, the ideal value for
the interval is 1950/6/4 = 81.25. However, if PLS_INTERVAL[7:0] = 82, the sixth output occurs too late and
would be lost. In this case, the proper value for PLS_INTERVAL[7:0] is 81 (i.e., round down the result).
Since one LSB of PLS_INTERVAL[7:0] is equal to 4 CK_FIR clock cycles, the pulse time interval T
I
in units of
CK_FIR clock cycles is:
T
I
= 4* PLS_INTERVAL[7:0]