Table 49, Table 50, Table 51 – Rainbow Electronics 71M6542G User Manual

Page 62

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© 2008–2011 Teridian Semiconductor Corporation

v1.1

Table 49: Data/Direction Registers for SEGDIO19 to SEGDIO27 (71M6541D/F)

SEGDIO

19 20

21 22

23 24 25 26 27

Pin #

16 15

14 13

12 11 10

9

8

Configuration:
0 = DIO, 1 = LCD

3

4

5

6

7

0

1

2

3

LCD_MAP[23:19] (I/O RAM 0x2409)

LCD_MAP[27:24] (I/O RAM 0x2408)

SEG Data Register

19 20

21 22

23 24 25 26 27

LCD_SEGDIO19[5:0] to LCD_SEGDIO27[5:0]

(I/O RAM 0x2423[5:0] to 0x242C[5:0])

DIO Data Register

19 20

21 22

23 24 25 26 27

LCD_SEGDIO19[0] to LCD_SEGDIO27[0]

(I/O RAM 0x2423[0] to 0x242C[0])

Direction Register:
0 = input, 1 = output

19 20

21 22

23 24 25 26 27

LCD_SEGDIO19[1] to LCD_SEGDIO27[1]

(I/O RAM 0x2423[1] to 0x242C[1])

Table 50: Data/Direction Registers for SEGDIO36-39 to SEGDIO44-45 (71M6541D/F)

SEGDIO

36

37

38

39

44

45

Pin #

3

2

1

64

63

62

Configuration:
0 = DIO, 1 = LCD

4

5

6

7

4

5

LCD_MAP[39:36]

(I/O RAM 0x2407)

LCD_MAP[45:44]

(I/O RAM 0x2406)

SEG Data Register

36

37

38

39

44

45

LCD_SEGDIO36[5:0] to LCD_SEGDIO45[5:0]

(I/O RAM 0x2434-2437[5:0] to 0x243C-243D[5:0])

DIO Data Register

36

37

38

39

44

45

LCD_SEGDIO32[0] to LCD_SEGDIO45[0]

(I/O RAM 0x2434-2437[0] to 0x243C-243D[0])

Direction Register:
0 = input, 1 = output

36

37

38

39

44

45

LCD_SEGDIO32[1] to LCD_SEGDIO45[1]

(I/O RAM 0x2434-2437[1] to 0x243C-243D[1])

Table 51: Data/Direction Registers for SEGDIO51 and SEGDIO55 (71M6541D/F)

SEGDIO

51

55

Pin #

33

32

Configuration:
0 = DIO, 1 = LCD

0

4

LCD_MAP[55], LDC_MAP[51]

(I/O RAM 0x2405)

SEG Data Register

51

55

LCD_SEGDIO51[5:0], LCD_SEGDIO55[5:0]

(I/O RAM 0x2443[5:0] and 0x2447[5:0])

DIO Data Register

51

55

LCD_SEGDIO51[0] to LCD_SEGDIO55[0]

(I/O RAM 0x2443[0] and 0x2447[0])

Direction Register:
0 = input, 1 = output

51

55

LCD_SEGDIO51[1] to LCD_SEGDIO55[1]

(I/O RAM 0x2443[1] and 0x2447[1])

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