Rainbow Electronics 71M6542G - Manual (Page 44)

44 © 2008–2011 Teridian Semiconductor Corporation v1.1
External MPU Interrupts
The seven external interrupts are the interrupts external to the 80515 core, i.e., signals that originate in
other parts of the 71M654x, for example the CE, DIO, RTC, or EEPROM interface.
The external interrupts are connected as shown in Table 32 . The polarity of interrupts 2 and 3 is
programmable in the MPU via the I3FR and I2FR bits in T2CON (SFR 0xC8). Interrupts 2 and 3 should be
programmed for falling sensitivity (I3FR = I2FR = 0). The generic 8051 MPU literature states that interrupts 4
through 6 are defined as rising-edge sensitive. Thus, the hardware signals attached to interrupts 5
and 6 are inverted to achieve the edge polarity shown in
Table 32 .
Table 32: External MPU Interrupts
External
Interrupt
Connection Polarity Flag Reset
0 Digital I/O see 2.5.8 automatic
1 Digital I/O see 2.5.8 automatic
2 CE_PULSE rising automatic
3 CE_BUSY falling automatic
4 VSTAT (VSTAT[2:0] changed) rising automatic
5 EEPROM busy (falling), SPI (rising) automatic
6 XFER_BUSY (falling), RTC_1SEC, RTC_1MIN, RTC_T falling manual
External interrupt 0 and 1 can be mapped to pins on the device using DIO resource maps. See
2.5.8
Digital I/O for more information.
SFR enable bits must be set to permit any of these interrupts to occur. Likewise, each interrupt has its own
flag bit, which is set by the interrupt hardware, and reset by the MPU interrupt handler. XFER_BUSY,
RTC_1SEC, RTC_1MIN, RTC_T, SPI, PLLRISE and PLLFALL have their own enable and flag bits in
addition to the interrupt 6, 4 and enable and flag bits (see
Table 33: Interrupt Enable and Flag Bits ).
IE0 through IEX6 are cleared automatically when the hardware vectors to the interrupt handler.
The other flags, IE_XFER through IE_VPULSE, are cleared by writing a zero to them.
Since these bits are in an SFR bit addressable byte, common practice would be to clear them
with a bit operation, but this must be avoided. The hardware implements bit operations as a
byte wide read-modify-write hardware macro. If an interrupt occurs after the read, but before
the write, its flag cleared unintentionally.
The proper way to clear the flag bits is to write a byte mask consisting of all ones except for a
zero in the location of the bit to be cleared. The flag bits are configured in hardware to ignore
ones written to them.
Table 33: Interrupt Enable and Flag Bits
Interrupt Enable Interrupt Flag
Interrupt Description
Name Location Name Location
EX0 SFR 0xA8[[0] IE0 SFR 0x88[1] External interrupt 0
EX1 SFR 0xA8[2] IE1 SFR 0x88[3] External interrupt 1
EX2 SFR 0xB8[1] IEX2 SFR 0xC0[1] External interrupt 2
EX3 SFR 0xB8[2] IEX3 SFR 0xC0[2] External interrupt 3
EX4 SFR 0xB8[3] IEX4 SFR 0xC0[3] External interrupt 4
EX5 SFR 0xB8[4] IEX5 SFR 0xC0[4] External interrupt 5
EX6 SFR 0xB8[5] IEX6 SFR 0xC0[5] External interrupt 6
EX_XFER
EX_RTC1S
EX_RTC1M
EX_RTCT
0x2700[0]
0x2700[1]
0x2700[2]
0x2700[4] IE_XFER
IE_RTC1S
IE_RTC1M
IE_RTCT
SFR 0xE8[0]
SFR 0xE8[1]
SFR E0x8[2]
SFR 0xE8[4] XFER_BUSY interrupt (int 6)
RTC_1SEC interrupt (int 6)
RTC_1MIN interrupt (int 6)
RTC_T alarm clock interrupt (int 6)