Rainbow Electronics 71M6542G - Manual (Page 28)

28 © 2008–2011 Teridian Semiconductor Corporation v1.1
If the FIFO is enabled (i.e., PLS_INTERVAL[7:0]
≠ 0), hardware also provides a maximum pulse width feature
in control register PLS_MAXWIDTH[7:0] (I/O RAM 0x210A) . By default, WPULSE and VPULSE are negative
pulses (i.e., low level pulses, designed to sink current through an LED). PLS_MAXWIDTH[7:0] determines the
maximum negative pulse width T
MAX
in units of CK_FIR clock cycles based on the pulse interval T
I
according to the formula:
T
MAX
= (2 * PLS_MAXWIDTH[7:0] + 1) * T
I
If PLS_MAXWIDTH = 255 or PLS_INTERVAL=0, no pulse width checking is performed, and the pulses
default to 50% duty cycle. T
MAX
is typically programmed to 10 ms., which works well with most calibration
systems.
The polarity of the pulses may be inverted with the control bit PLS_INV (I/O RAM 0x210C[0]). When
PLS_INV is set, the pulses are active high. The default value for PLS_INV is zero, which selects active low
pulses.
The WPULSE and VPULSE pulse generator outputs are available on pins SEGDIO0/WPULSE and
SEGDIO1/VPULSE, respectively (pins 45 and 44). The pulses can also be output on OPT_TX pin 53
(see OPT_TXE[1:0], I/O RAM 0x2456[3:2] for details).
Figure 12. Pulse Generator FIFO Timing
2.3.7 CE Functional Overview
The 71M654x provides an ADC and multiplexer to sample the analog currents and voltages as seen in
Figure 2 and Figure 3 . The VA and VB voltage sensors are formed by resistive voltage dividers directly
connected to the 71M654x device, and therefore always use the ADC and multiplexer facilities in the
71M654x device. Current sensors, however, may be connected directly to the 71M654x or remotely
connected through an isolated 71M6x01 device. The remote 71M6x01 sensor has its own separate ADC
and voltage reference. When a current sensor is connected via a 71M6x01 isolated sensor, the 71M654x
places the sample data received digitally over the isolation interface (via the pulse transformer) in the
appropriate CE RAM location, as shown in
Figure 3 . The ADCs (i.e., ADC in the 71M654x and the ADC in
the 71M6x01) process their corresponding sensor channels providing one sample per channel per
multiplexer cycle.
Figure 14 (71M6541D/F) and Figure 15 (71M6542F) show the sampling sequence when both current
sensors (IA and IB) are connected directly to the 71M6541D/F as seen in Figure 2 . However, when the IB
CK32
MUX_DIV Conversions ( MUX_DIV =4 is shown) Settle
ADC MUX Frame
MUX_SYNC
150
WPULSE
S
0
S
1
S
2
S
3
S
4
S
5
CE CODE
RST
W_FIFO
S
0
S
1
S
2
S
3
S
4
S
5
S
0
S
1
S
2
S
3
S
4
S
5
4*PLS_INTERVAL
2. If WPULSE is low longer than (2*PLS_MAXWIDTH+1) updates, WPULSE will be raised until the next
low-going pulse begins.
3. Only the WPULSE circuit is shown. The VARPULSE circuit behaves identically.
4. All dimensions are in CK_FIR cycles (4.92MHz).
5. If PLS_INTERVAL=0, FIFO does not perform delay.
4*PLS_INTERVAL 4*PLS_INTERVAL 4*PLS_INTERVAL 4*PLS_INTERVAL 4*PLS_INTERVAL
1. This example shows how the FIFO distributes 6 pulse generator updates over one MUX frame.