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© 2008–2011 Teridian Semiconductor Corporation
v1.1
Tables
Table 1. Required CE Code and Settings for Local Sensors ................................................................... 15
Table 2. Required CE Code and Settings for 71M6x01 isolated Sensor ................................................. 15
Table 3: ADC Input Configuration ......................................................................................................... 17
Table 4: Multiplexer and ADC Configuration Bits ................................................................................... 19
Table 5. RCMD[4:0] Bits ........................................................................................................................ 22
Table 6: Remote Interface Read Commands ........................................................................................ 23
Table 7: I/O RAM Control Bits for Isolated Sensor ................................................................................. 23
Table 8: Inputs Selected in Multiplexer Cycles ....................................................................................... 25
Table 9: CKMPU Clock Frequencies ...................................................................................................... 31
Table 10: Memory Map .......................................................................................................................... 32
Table 11: Internal Data Memory Map ..................................................................................................... 33
Table 12: Special Function Register Map ............................................................................................... 33
Table 13: Generic 80515 SFRs - Location and Reset Values ................................................................. 34
Table 14: PSW Bit Functions (SFR 0xD0) ................................................................................................. 35
Table 15: Port Registers (SEGDIO0-15) ................................................................................................ 36
Table 16: Stretch Memory Cycle Width .................................................................................................. 36
Table 18: Baud Rate Generation............................................................................................................ 37
Table 19: UART Modes ......................................................................................................................... 37
Table 20: The S0CON (UART0) Register (SFR 0x98) ............................................................................. 38
Table 21: The S1CON (UART1) Register (SFR 0x9B) ............................................................................. 38
Table 22: PCON Register Bit Description (SFR 0x87) ............................................................................ 39
Table 23: Timers/Counters Mode Description ........................................................................................ 39
Table 24: Allowed Timer/Counter Mode Combinations ........................................................................... 39
Table 25: TMOD Register Bit Description (SFR 0x89) ............................................................................ 40
Table 26: The TCON Register Bit Functions (SFR 0x88) ........................................................................ 40
Table 27: The IEN0 Bit Functions (SFR 0xA8) ........................................................................................ 41
Table 28: The IEN1 Bit Functions (SFR 0xB8) ........................................................................................ 41
Table 29: The IEN2 Bit Functions (SFR 0x9A) ........................................................................................ 42
Table 30: TCON Bit Functions (SFR 0x88) ............................................................................................. 42
Table 31: The T2CON Bit Functions (SFR 0xC8) ................................................................................... 42
Table 32: The IRCON Bit Functions (SFR 0xC0) .................................................................................... 42
Table 33: External MPU Interrupts ......................................................................................................... 44
Table 34: Interrupt Enable and Flag Bits ............................................................................................... 44
Table 35: Interrupt Priority Level Groups ................................................................................................ 45
Table 36: Interrupt Priority Levels .......................................................................................................... 45
Table 37: Interrupt Priority Registers (IP0 and IP1) ................................................................................. 45
Table 38: Interrupt Polling Sequence ..................................................................................................... 46
Table 39: Interrupt Vectors .................................................................................................................... 46
Table 40: Flash Memory Access ............................................................................................................ 48
Table 41: Flash Security ........................................................................................................................ 49
Table 42: Clock System Summary ......................................................................................................... 51
Table 43: RTC Control Registers ........................................................................................................... 52
Table 44: I/O RAM Registers for RTC Temperature Compensation ........................................................ 53
Table 45: NV RAM Temperature Table Structure ................................................................................... 54
Table 46: I/O RAM Registers for RTC Interrupts .................................................................................... 55
Table 47: I/O RAM Registers for Temperature and Battery Measurement .............................................. 56
Table 48: Selectable Resources using the DIO_Rn[2:0] Bits................................................................... 59
Table 49: Data/Direction Registers for SEGDIO0 to SEGDIO14 (71M6541D/F)...................................... 61
Table 50: Data/Direction Registers for SEGDIO19 to SEGDIO27 (71M6541D/F).................................... 62
Table 51: Data/Direction Registers for SEGDIO36-39 to SEGDIO44-45 (71M6541D/F) .......................... 62
Table 52: Data/Direction Registers for SEGDIO51 and SEGDIO55 (71M6541D/F) ................................. 62
Table 53: Data/Direction Registers for SEGDIO0 to SEGDIO15 (71M6542F) ......................................... 63
