v1.1
© 2008–2011 Teridian Semiconductor Corporation
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Table 54: Data/Direction Registers for SEGDIO16 to SEGDIO31 (71M6542F) ....................................... 64
Table 55: Data/Direction Registers for SEGDIO32 to SEGDIO45 (71M6542F) ....................................... 64
Table 56: Data/Direction Registers for SEGDIO51 to SEGDIO55 (71M6542F) ....................................... 64
Table 57: LCD_VMODE[1:0] Configurations .......................................................................................... 65
Table 58: LCD Configurations ............................................................................................................... 67
Table 59: 71M6541D/F LCD Data Registers for SEG46 to SEG50 ......................................................... 69
Table 60: 71M6542F LCD Data Registers for SEG46 to SEG50 ............................................................ 70
Table 61: EECTRL Bits for 2-pin Interface ............................................................................................... 71
Table 62: EECTRL Bits for the 3-wire Interface ....................................................................................... 71
Table 63: SPI Transaction Fields ........................................................................................................... 74
Table 64: SPI Command Sequences ..................................................................................................... 75
Table 65: SPI Registers ......................................................................................................................... 76
Table 66: TMUX[5:0] Selections ............................................................................................................ 79
Table 67: TMUX2[4:0] Selections ........................................................................................................... 79
Table 68: Available Circuit Functions ..................................................................................................... 82
Table 69: VSTAT[2:0] (SFR 0xF9[2:0]) .................................................................................................... 85
Table 70: Wake Enables and Flag Bits .................................................................................................. 87
Table 71: Wake Bits .............................................................................................................................. 89
Table 72: Clear Events for WAKE flags .................................................................................................. 90
Table 73: GAIN_ADJn Compensation Channels .................................................................................... 98
Table 74: GAIN_ADJn Compensation Channels .................................................................................. 100
Table 75: I/O RAM Map – Functional Order, Basic Configuration ......................................................... 105
Table 76: I/O RAM Map – Functional Order ......................................................................................... 107
Table 77: I/O RAM Map – Functional Order ......................................................................................... 111
Table 78. Standard CE Codes ............................................................................................................. 125
Table 79: CE EQU Equations and Element Input Mapping ................................................................... 126
Table 80: CE Raw Data Access Locations ........................................................................................... 127
Table 81: CESTATUS Register .............................................................................................................. 127
Table 82: CESTATUS (CE RAM 0x80) Bit Definitions .............................................................................. 128
Table 83: CECONFIG Register ............................................................................................................. 128
Table 84: CECONFIG (CE RAM 0x20) Bit Definitions ............................................................................. 128
Table 85: Sag Threshold and Gain Adjust Control ................................................................................ 129
Table 86: CE Transfer Variables (with Local Sensors).......................................................................... 130
Table 87: CE Transfer Variables (with Remote Sensor) ....................................................................... 130
Table 88: CE Energy Measurement Variables (with Local Sensors) ..................................................... 131
Table 89: CE Energy Measurement Variables (with Remote Sensor) ................................................... 131
Table 90: Other Transfer Variables ...................................................................................................... 132
Table 91: CE Pulse Generation Parameters......................................................................................... 132
Table 92: CE Parameters for Noise Suppression and Code Version..................................................... 134
Table 93: CE Calibration Parameters ................................................................................................... 135
Table 94: Absolute Maximum Ratings .................................................................................................. 138
Table 95: Recommended External Components .................................................................................. 139
Table 96: Recommended Operating Conditions ................................................................................... 139
Table 97: Input Logic Levels ................................................................................................................ 140
Table 98: Output Logic Levels ............................................................................................................. 140
Table 99
: Battery Monitor Performance Specifications (TEMP_BAT= 1) ................................................ 141
Table 100. Temperature Monitor .......................................................................................................... 141
Table 101: Supply Current Performance Specifications ........................................................................ 142
Table 102: V3P3D Switch Performance Specifications ......................................................................... 143
Table 103. Internal Power Fault Comparator Specifications ................................................................. 143
Table 104: 2.5 V Voltage Regulator Performance Specifications .......................................................... 143
Table 105: Low-Power Voltage Regulator Performance Specifications ................................................. 144
Table 106: Crystal Oscillator Performance Specifications ..................................................................... 144
