Rainbow Electronics 71M6542G - Manual (Page 31)

v1.1 © 2008–2011 Teridian Semiconductor Corporation 31
2.4 80515 MPU Core
The 71M6541D/F and 71M6542F include an 80515 MPU (8-bit, 8051-compatible) that processes most
instructions in one clock cycle. Using a 4.9 MHz clock results in a processing throughput of 4.9 MIPS. The
80515 architecture eliminates redundant bus states and implements parallel execution of fetch and execution
phases. Normally, a machine cycle is aligned with a memory fetch, therefore, most of the 1-byte instructions
are performed in a single machine cycle (MPU clock cycle). This leads to an 8x average performance
improvement (in terms of MIPS) over the Intel

8051 device running at the same clock frequency.
Table 9 shows the CKMPU frequency as a function of the MCK clock (19.6608 MHz) divided by the MPU
clock divider which is set in the I/O RAM control field MPU_DIV[2:0] (I/O RAM 0x2200[2:0]). Actual processor
clocking speed can be adjusted to the total processing demand of the application (metering calculations,
AMR management, memory management, LCD driver management and I/O management) using
MPU_DIV[2:0], as shown in
Table 9 .
Table 9: CKMPU Clock Frequencies
MPU_DIV [2:0] CKMPU Frequency
000 4.9152 MHz
001 2.4576 MHz
010 1.2288 MHz
011 614.4 kHz
100
307.2 kHz
101
110
111
Typical measurement and metering functions based on the results provided by the internal 32-bit compute
engine (CE) are available for the MPU as part of the Teridian standard library. Teridian provides
demonstration source code to help reduce the design cycle.
2.4.1 Memory Organization and Addressing
The 80515 MPU core incorporates the Harvard architecture with separate code and data spaces. Memory
organization in the 80515 is similar to that of the industry standard 8051. There are three memory areas:
Program memory (Flash, shared by MPU and CE), external RAM (Data RAM, shared by the CE and MPU,
Configuration or I/O RAM), and internal data memory (Internal RAM).
Table 10 shows the memory map.
Program Memory
The 80515 can address up to 64 KB of program memory space (0x0000 to 0xFFFF). Program memory is
read when the MPU fetches instructions or performs a MOVC operation.
After reset, the MPU starts program execution from program memory location 0x0000. The lower part of
the program memory includes reset and interrupt vectors. The interrupt vectors are spaced at 8-byte
intervals, starting from 0x0003.
MPU External Data Memory (XRAM)
Both internal and external memory is physically located on the 71M654x device. The external memory
referred in this documentation is only external to the 80515 MPU core.
3 KB of RAM starting at address 0x0000 is shared by the CE and MPU. The CE normally uses the first
1 KB, leaving 2 KB for the MPU. Different versions of the CE code use varying amounts. Consult the
documentation for the specific code version being used for the exact limit.
If the MPU overwrites the CE’s working RAM, the CE’s output may be corrupted. If the CE is
disabled, the first 0x40 bytes of RAM are still unusable while MUX_DIV[3:0]
≠ 0 because the
71M654x ADC writes to these locations. Setting MUX_DIV[3:0] = 0 disables the ADC output
preventing the CE from writing the first 0x40 bytes of RAM.
In addition, MUXn_SEL[3:0] values must be written only after writing MUX_DIV[3:0].