Moog Crossbow NAV440 Series - Manual (Page 37)

NAV440 User Manual
7430‐0131‐01 Rev. F
Page 37
Signals
Extern ) al GPS Aiding (Port B, VG440 and AHRS440
NOTE: This feature only applies to VG440 and AHRS440.
NOTE: The GPS serial communication port should be configured to 8 data bits, 1 start bit, 1 stop bit, no parity bit,
and no flow control.
The VG440/AHRS440 allows using an external GPS receiver. To do so, the following actions are required:
• The external GPS receiver must be configured to output the GPS messages to be compatible with the 440
Series . Table 10 below shows the supported GPS protocols and guidelines for configuration. The details of
the GPS messages can be found in the respective GPS protocol documents.
• The VG/AHRS440 must be configured to accept external GPS information. Refer to Table 10 below and
Chapter 7. Configuring the 440 Series with NAV­VIEW 2.2.
Table 10 Configuration for External GPS Receiver for VG440/AHRS440
Protocols Required Messages Required Message Rate Baud rate
Ublox binary NAV‐LLH, NAV‐VELNED,
NAV‐STATUS
4 Hz 9600, 19200, 38400, 57600 $
NovAtel OEM4
OEMV Binary
and BestPosB, BestVelB 4Hz 9600, 19200, 38400, 57600 $
NovAtel
ASCII OEM4 PosVelNavDopA 4Hz 19200, 38400, 57600 $
NMEA* GPGGA, GPVTG 4Hz 9600, 19200, 38400, 57600 $
* Not recommended for airborne applications.
$ 57600 is the preferred baud rate for optimum performance
If the VG/AHRS440 is parsing valid external GPS data and the GPS receiver has 3D lock, then the
Chapter 11. Built In Test (BIT) comStatusÆnoExternalGPS flag will be zero, otherwise it will be one. Refer to on page
93 for details about system status indications.
As the NMEA protocol does not provide vertical velocity, the vertical velocity the 440 Series estimates (based upon
GPS altitude changes) may not be sufficient for airborne applications.
NOTE: The NMEA protocol is not recommended for airborne applications
Hardware BIT Error Output
The hardware BIT error output pin is the ultimate indication of system failure. This indication is available in most
software output packets as the master Fail flag. It is the logical AND of the hardware Error, com Error, and software
Error flags monitored by the system. In the event of a communication failure, the hardware BIT error pin may be
used to detect a master Fail assertion. This pin is open‐collector and requires a 1k to 10k ohm pull‐up resister. The
system will drive this pin low to assert a system failure.