Altera Hybrid Memory Cube Controller - Manual (Page 2)

Contents
About the Altera Hybrid Memory Cube Controller IP Core.............................1-1
HMC Controller IP Core Supported Features.........................................................................................1-2
HMC Controller IP Core Supported HMC Transaction Types............................................................1-3
Device Family Support................................................................................................................................1-4
IP Core Verification.....................................................................................................................................1-4
Simulation.........................................................................................................................................1-5
Hardware Testing.............................................................................................................................1-5
Performance and Resource Utilization.....................................................................................................1-5
Device Speed Grade Support......................................................................................................................1-6
Release Information.....................................................................................................................................1-6
Getting Started with the HMC Controller IP Core............................................ 2-1
Installing and Licensing IP Cores..............................................................................................................2-2
OpenCore Plus IP Evaluation........................................................................................................ 2-2
Specifying IP Core Parameters and Options............................................................................................2-2
HMC Controller IP Core Parameters....................................................................................................... 2-3
RX Mapping and TX Mapping Parameters..................................................................................2-5
Files Generated for Altera IP Cores...........................................................................................................2-8
Integrating Your IP Core in Your Design................................................................................................ 2-9
Pin Constraints.................................................................................................................................2-9
Required External Blocks..............................................................................................................2-10
Simulating Altera IP Cores in other EDA Tools................................................................................... 2-16
Understanding the Testbench..................................................................................................................2-18
Generating and Running the Testbench.................................................................................................2-18
Functional Description....................................................................................... 3-1
High Level Block Diagram..........................................................................................................................3-1
Interfaces Overview..................................................................................................................................... 3-2
Application Interfaces..................................................................................................................... 3-2
HMC Interface..................................................................................................................................3-2
Interface to External I 2 C Master.................................................................................................... 3-3
Control and Status Register Interface........................................................................................... 3-3
Status and Debug Interface.............................................................................................................3-3
Transceiver Control Interfaces.......................................................................................................3-3
Clocking and Reset Structure.....................................................................................................................3-4
Initialization..................................................................................................................................................3-5
M20K ECC Support.....................................................................................................................................3-6
Flow Control.................................................................................................................................................3-7
Error Detection and Management.............................................................................................................3-7
Testing Features........................................................................................................................................... 3-8
TOC-2 About the Altera Hybrid Memory Cube Controller IP Core
Altera Corporation