Functional description, High level block diagram, Functional description -1 – Altera Hybrid Memory Cube Controller User Manual
Page 29: High level block diagram -1
Functional Description
3
2015.05.04
UG-01152
The Altera HMC Controller MegaCore IP core enables easy access to external HMC devices.
High Level Block Diagram
Figure 3-1: HMC Controller IP Core Block Diagram
HMC Controller IP Core
TX
FIFO
Link
Master
Link
Slave
256- or 512-Bit Data
256- or 512-Bit Data
Control and
Status Block
Initialization
Initialization
State Machine
State Machine
Arria 10
Transceiver
Reconfiguration
Block
Avalon-MM
TX Lane
Swapper
RX Lane
Swapper
Avalon-MM
Interface to PLL IP Cores
to HMC device
from HMC device
Transceiver
x8
or
x16
Application
Interfaces
Control and Status
Interface
Arria 10 Transceiver
Dynamic Reconfiguration
Interface
Interface to
I C Master
2
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